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preliminary user?s manual NB85E 32-bit microprocessor core hardware document no. a13971ej7v1um00 (7th edition) date published january 2002 ns cp(n) printed in japan 1998 ? 1999
preliminary user?s manual a13971ej7v0um 2 [memo]
preliminary user?s manual a13971ej7v0um 3 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
preliminary user?s manual a13971ej7v0um 4 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. ? the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. ? not all devices/types available in every country. please check with local nec representative for availability and additional information. ? no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. ? nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, c opyrights or other intellectual property rights of nec corporation or others. ? descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. ? while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. ? nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m5d 98. 12
preliminary user?s manual a13971ej7v0um 5 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j01.12 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 ? branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 ? branch sweden taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (france) s.a. v lizy-villacoublay, france tel: 01-3067-58-00 fax: 01-3067-58-99 nec electronics (france) s.a. representaci?n en espa?a madrid, spain tel: 091-504-27-87 fax: 091-504-28-60
preliminary user?s manual a13971ej7v0um 6 major revisions in this edition pages description p. 28 modification of 2.2.1 (3) vpwrite p. 30 modification of 2.2.2 (12) vbseq2 to vbseq0 p. 32 modification of 2.2.2 (17) vbdc p. 33 modification of 2.2.4 (1) idmastp p. 34 modification of 2.2.7 (1) irama27 to irama2 p. 43 modification of 2.3 recommended connection of unused pins p. 63 modification of figure 3-11 peripheral i/o area p. 94 addition of figure to caution in 4.9.2 (6) transfer status p. 108 addition of 4.9.5 (1) bus priority p. 131 addition of caution 2 to 6.2.1 power save control register (psc) p. 134 modification of 6.4 (2) (a) cancellation by interrupt request p. 136 addition of remark to 6.5 (1) setting and operation status p. 141 modification of figure 6-6 hardware stop mode set/cancel timing example p. 163 modification of 7.8.4 block transfer mode p. 165 modification of 7.9.2 flyby transfer p. 219 modification of 8.7 periods when interrupts cannot be acknowledged p. 226 modification of 9.4 (2) test mode pins the mark shows major revised points.
preliminary user?s manual a13971ej7v0um 7 preface target readers this manual is intended for users who wish to understand the hardware functions of the NB85E, which is the cpu core of a cell-based ic (cbic), to design application systems using the NB85E. purpose this manual is designed to help users understand the hardware functions of the NB85E outlined in organization below. organization this manual describes the hardware functions of the NB85E. for details about the architecture and instruction functions, refer to the ?v850e1 user?s manual architecture.? the organization of each manual is as follows: NB85E user?s manual v850e1 user?s manual hardware (this manual) architecture ? overview ? register set ? cpu function ? instruction format and instruction set ? peripheral i/o functions ? interrupts and exceptions ? test functions ? pipeline operation how to read this manual it is assumed that the readers of this manual have general knowledge of electricity, logic circuits, and microcontrollers. to gain a general understanding of the hardware functions of the NB85E read this manual according to the contents. to confirm details of a function, etc. when the name is known refer to appendix b index . to learn about the details of an instruction function refer to the v850e1 user?s manual architecture . conventions data significance: higher digits on the left and lower digits on the right active low representation: xxxz (z after pin or si gnal name) note: footnote for item marked with note in the text caution: information requiring particular attention remark: supplementary information numerical representation: binary ? xxxx or xxxxb decimal ? xxxx hexadecimal ? xxxxh prefix indicating the power of 2 (address space, memory capacity): k (kilo) ? 2 10 = 1024 m (mega) ? 2 20 = 1024 2 g (giga) ? 2 30 = 1024 3 data type: word ? 32 bits halfword ? 16 bits byte ? 8 bits
preliminary user?s manual a13971ej7v0um 8 related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. ? v850e1 user?s manual architecture (u14559e) ? NB85Et user?s manual hardware (a14342e) ? memory controller user?s manual NB85E, NB85Et (a14206e) ? instruction cache, data cache user?s manual NB85E, NB85Et (a14247e) ? npb peripheral macro user?s manual NB85E, NB85Et (a14005e) ? cb-9 family vx/vm type design manual NB85E, NB85Et (a14335e) ? cb-9 family vx/vm type core library design manual cpu core, memory controller (a13195e) the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
preliminary user?s manual a13971ej7v0um 9 contents chapter 1 introduction................................................................................................................... .17 1.1 outline ................................................................................................................... ........................... 17 1.2 application system ........................................................................................................ ................. 18 1.3 features.................................................................................................................. .......................... 19 1.4 symbol diagram ............................................................................................................ .................. 21 1.5 function blocks........................................................................................................... .................... 22 1.5.1 internal block diagram.................................................................................................. ............................... 22 1.5.2 internal units .......................................................................................................... ..................................... 23 chapter 2 pin functions ....................................................................................................... ............24 2.1 list of pin functions ..................................................................................................... .................. 24 2.2 explanation of pin functions .............................................................................................. ........... 28 2.2.1 npb pins ................................................................................................................ ..................................... 28 2.2.2 vsb pins ................................................................................................................ ..................................... 28 2.2.3 system control pins..................................................................................................... ................................ 32 2.2.4 dmac pins ............................................................................................................... ................................... 33 2.2.5 intc pins ............................................................................................................... ..................................... 34 2.2.6 vfb pins ................................................................................................................ ..................................... 34 2.2.7 vdb pins ................................................................................................................ ..................................... 34 2.2.8 instruction cache pins .................................................................................................. ............................... 35 2.2.9 data cache pins ......................................................................................................... ................................. 36 2.2.10 rcu pins............................................................................................................... .................................... 38 2.2.11 peripheral evaluation chip mode pins ................................................................................... .................... 38 2.2.12 operation mode setting pins ............................................................................................ ......................... 39 2.2.13 test mode pins ......................................................................................................... ................................ 42 2.3 recommended connection of unused pins................................................................................. 43 2.4 pin status ................................................................................................................ ......................... 45 chapter 3 cpu................................................................................................................. .......................48 3.1 features.................................................................................................................. .......................... 48 3.2 registers ................................................................................................................. ......................... 49 3.2.1 program registers ....................................................................................................... ................................ 50 3.2.2 system registers ........................................................................................................ ................................. 52 3.3 address space............................................................................................................. .................... 55 3.3.1 program area ............................................................................................................ .................................. 56 3.3.2 data area ............................................................................................................... ..................................... 57 3.4 areas ..................................................................................................................... ............................ 59 3.4.1 rom area................................................................................................................ .................................... 59 3.4.2 ram area ................................................................................................................ .................................... 61 3.4.3 peripheral i/o area..................................................................................................... ................................. 62 3.4.4 external memory area.................................................................................................... ............................. 64 3.5 peripheral i/o registers .................................................................................................. ................ 64 3.5.1 NB85E control registers ................................................................................................. ............................. 65 3.5.2 memory controller (memc) control registers.............................................................................. ................. 68 3.5.3 instruction cache control registers ..................................................................................... ......................... 69 3.5.4 data cache control registers ............................................................................................ ........................... 69
preliminary user?s manual a13971ej7v0um 10 3.6 NB85E901 (rcu) interface .................................................................................................. ............ 70 3.6.1 outline................................................................................................................. ........................................ 70 3.6.2 on-chip debugging....................................................................................................... ............................... 70 chapter 4 bcu................................................................................................................. ...................... 71 4.1 features .................................................................................................................. .......................... 71 4.2 memory banks .............................................................................................................. ................... 71 4.3 programmable chip select function ......................................................................................... .... 74 4.4 programmable peripheral i/o area selection function ............................................................... 80 4.5 bus size setting function ................................................................................................. ............. 83 4.6 endian setting function ................................................................................................... .............. 84 4.6.1 usage restrictions concerning big endian format with nec development tools .......................................... 85 4.7 cache configuration....................................................................................................... ................. 87 4.8 bcu-related register setting examples ..................................................................................... .88 4.9 data transfer using vsb ................................................................................................... ............. 91 4.9.1 data transfer example ................................................................................................... .............................. 91 4.9.2 control signals ......................................................................................................... ................................... 92 4.9.3 read/write timing ....................................................................................................... ................................. 94 4.9.4 reset timing ............................................................................................................ .................................. 107 4.9.5 bus master transition ................................................................................................... ............................. 108 4.9.6 misalign access timing .................................................................................................. ............................ 112 chapter 5 bbr................................................................................................................. .................... 114 5.1 programmable peripheral i/o area.......................................................................................... ..... 116 5.2 wait insertion function ................................................................................................... .............. 119 5.3 retry function............................................................................................................ .................... 121 5.4 npb read/write timing..................................................................................................... ............ 122 chapter 6 stbc................................................................................................................ ................... 129 6.1 power save function ....................................................................................................... ............. 129 6.2 control registers......................................................................................................... .................. 130 6.2.1 power save control register (psc) ....................................................................................... ..................... 130 6.2.2 command register (prcmd) ................................................................................................ .................... 132 6.3 halt mode ................................................................................................................. .................... 133 6.4 software stop mode ........................................................................................................ ............ 134 6.5 hardware stop mode ........................................................................................................ ........... 136 6.6 clock control in software/hardware stop mode ...................................................................... 137 chapter 7 dmac................................................................................................................ .................. 142 7.1 features .................................................................................................................. ........................ 142 7.2 configuration ............................................................................................................. .................... 143 7.3 transfer objects .......................................................................................................... .................. 144 7.4 dma channel priorities .................................................................................................... ............. 144 7.5 control registers......................................................................................................... .................. 145 7.5.1 dma source address registers 0 to 3 (dsa0 to dsa3)...................................................................... ....... 145 7.5.2 dma destination address registers 0 to 3 (dda0 to dda3)................................................................. ..... 147 7.5.3 dma transfer count registers 0 to 3 (dbc0 to dbc3) ...................................................................... ......... 149 7.5.4 dma addressing control registers 0 to 3 (dadc0 to dadc3)................................................................ ... 150
preliminary user?s manual a13971ej7v0um 11 7.5.5 dma channel control registers 0 to 3 (dchc0 to dchc3) ................................................................... .... 152 7.5.6 dma disable status register (ddis) ...................................................................................... .................... 153 7.5.7 dma restart register (drst) ............................................................................................. ........................ 153 7.6 next address setting function ............................................................................................. ....... 154 7.7 dma bus state ............................................................................................................. .................. 155 7.7.1 bus state types ......................................................................................................... ................................ 155 7.7.2 dmac bus cycle state transitions ........................................................................................ ..................... 157 7.8 transfer modes............................................................................................................ .................. 158 7.8.1 single transfer mode.................................................................................................... ............................. 158 7.8.2 single-step transfer mode............................................................................................... .......................... 160 7.8.3 line transfer mode ...................................................................................................... .............................. 161 7.8.4 block transfer mode ..................................................................................................... ............................. 163 7.8.5 one-time transfer when executing single transfers using dmarqn signal............................................... 164 7.9 transfer types............................................................................................................ ................... 165 7.9.1 two-cycle transfer...................................................................................................... ............................... 165 7.9.2 flyby transfer .......................................................................................................... .................................. 165 7.10 dma transfer start factors............................................................................................... ......... 165 7.11 output when dma transfer is complete.................................................................................. 166 7.12 forcible interruption .................................................................................................... ............... 167 7.13 forcible termination ..................................................................................................... .............. 168 7.14 dma transfer timing examples ............................................................................................. ... 170 7.15 precautions .............................................................................................................. .................... 194 chapter 8 intc................................................................................................................ .....................196 8.1 features.................................................................................................................. ........................ 196 8.2 non-maskable interrupts (nmi) ............................................................................................. ....... 199 8.2.1 operation ............................................................................................................... ................................... 202 8.2.2 restore ................................................................................................................. .................................... 203 8.3 maskable interrupts....................................................................................................... ................ 204 8.3.1 operation ............................................................................................................... ................................... 204 8.3.2 restore ................................................................................................................. .................................... 206 8.3.3 maskable interrupt priorities........................................................................................... ........................... 207 8.3.4 control registers....................................................................................................... ................................. 211 8.3.5 maskable interrupt status flag (id) ..................................................................................... ....................... 214 8.4 software exception ........................................................................................................ ............... 215 8.4.1 operation ............................................................................................................... ................................... 215 8.4.2 restore ................................................................................................................. .................................... 216 8.5 exception trap............................................................................................................ ................... 217 8.5.1 illegal opcode.......................................................................................................... .................................. 217 8.5.2 operation ............................................................................................................... ................................... 218 8.5.3 restore ................................................................................................................. .................................... 218 8.6 interrupt response time ................................................................................................... ........... 219 8.7 periods when interrupts cannot be acknowledged ................................................................. 219 chapter 9 test function ....................................................................................................... .........220 9.1 test pins................................................................................................................. ........................ 220 9.1.1 test bus pins (tbi39 to tbi0 and tbo34 to tbo0)......................................................................... ......... 220 9.1.2 bunri and test pins ..................................................................................................... ......................... 220
preliminary user?s manual a13971ej7v0um 12 9.2 list of test interface signals............................................................................................ ............ 221 9.3 example of connection of peripheral macro in test mode ....................................................... 222 9.4 handling of each pin in test mode......................................................................................... ..... 224 chapter 10 NB85E901 ........................................................................................................... .............. 227 10.1 overview ................................................................................................................. ...................... 227 10.1.1 symbol diagram ......................................................................................................... ............................. 227 10.2 pin functions ............................................................................................................ ................... 228 10.2.1 pin function list ...................................................................................................... .................................. 228 10.2.2 pin functions.......................................................................................................... .................................. 229 10.2.3 recommended connection of unused pins .................................................................................. ........... 232 10.2.4 pin status ............................................................................................................. ................................... 233 10.3 dubug function ........................................................................................................... ................ 235 10.4 NB85E connection example................................................................................................. ...... 236 10.5 n-wire type ie connection................................................................................................ ......... 237 10.5.1 ie connector (target system side) ...................................................................................... ..................... 237 10.5.2 example of recommended circuit when connecting NB85E901 and NB85E .......................................... 239 appendix a rom/ram access timing ............................................................................................ 24 0 appendix b index .............................................................................................................. .................. 242 appendix c revision history................................................................................................... ...... 247
preliminary user?s manual a13971ej7v0um 13 list of figures (1/3) figure no. title page 1-1 application system example .................................................................................................. ..................18 2-1 acknowledgement of dcresz signal ............................................................................................ .........32 3-1 list of cpu registers ....................................................................................................... ........................49 3-2 program counter (pc)........................................................................................................ ......................51 3-3 interrupt source register (ecr) ............................................................................................. .................53 3-4 program status word (psw) ................................................................................................... ................54 3-5 address space ............................................................................................................... ..........................55 3-6 program area ................................................................................................................ ...........................56 3-7 data area (64 mb mode)...................................................................................................... ....................57 3-8 data area (256 mb mode)..................................................................................................... ...................58 3-9 rom area.................................................................................................................... .............................59 3-10 ram area ................................................................................................................... ..............................61 3-11 peripheral i/o area........................................................................................................ ...........................63 3-12 connection of NB85E and n-wire type in-circuit emulator via rcu......................................................70 4-1 chip area select control register 0 (csc0).................................................................................. ..........74 4-2 chip area select control register 1 (csc1).................................................................................. ..........75 4-3 csc0 and csc1 register setting example (64 mb mode) .....................................................................76 4-4 csc0 and csc1 register setting example (256 mb mode) ...................................................................79 4-5 peripheral i/o area and programmable peripheral i/o area ...................................................................8 1 4-6 peripheral i/o area select control register (bpc) ........................................................................... .......82 4-7 bus size configuration register (bsc)....................................................................................... .............83 4-8 endian configuration register (bec)......................................................................................... ..............84 4-9 word data little endian format example ...................................................................................... ..........85 4-10 word data big endian format example ........................................................................................ ..........85 4-11 cache configuration register (bhc) ......................................................................................... ..............87 4-12 bpc, bsc, bec, bhc register setting example ................................................................................ ....88 4-13 example of data transfer using vsb ......................................................................................... .............91 4-14 read/write timing of bus slave connected to vsb ............................................................................ ....95 4-15 reset timing ............................................................................................................... ...........................107 4-16 bus arbitration timing (NB85E external master device) ...................................................................109 4-17 bus arbitration timing (external master device NB85E) ...................................................................111 4-18 misalign access timing ..................................................................................................... .....................112 5-1 npb connection overview ..................................................................................................... ................114 5-2 NB85E and peripheral macro connection example............................................................................... 115 5-3 peripheral i/o area and programmable peripheral i/o area .................................................................116 5-4 peripheral i/o area select control register (bpc) ........................................................................... .....117 5-5 bpc register setting example................................................................................................ ...............118 5-6 npb strobe wait control register (vswc) ..................................................................................... ......119 5-7 retry function .............................................................................................................. ..........................121 5-8 halfword access timing ...................................................................................................... ...................122 5-9 timing of byte access to odd address ........................................................................................ ..........123
preliminary user?s manual a13971ej7v0um 14 list of figures (2/3) figure no. title page 5-10 timing of byte access to even address...................................................................................... .......... 123 5-11 read modify write timing ................................................................................................... .................. 124 5-12 retry timing (write) ....................................................................................................... ....................... 124 5-13 retry timing (read) ........................................................................................................ ...................... 125 5-14 read/write timing of bus slave connected to npb ............................................................................ . 126 6-1 power save function state transition diagram ................................................................................ .... 129 6-2 power save control register (psc)........................................................................................... ........... 130 6-3 command register (prcmd) .................................................................................................... ........... 132 6-4 connection of NB85E and clock control circuit ............................................................................... .... 137 6-5 software stop mode set/cancel timing example............................................................................... 1 39 6-6 hardware stop mode set/cancel timing example ............................................................................. 141 7-1 dma source address registers 0h to 3h (dsa0h to dsa3h)............................................................. 145 7-2 dma source address registers 0l to 3l (dsa0l to dsa3l) ............................................................... 146 7-3 dma destination address registers 0h to 3h (dda0h to dda3h)...................................................... 147 7-4 dma destination address registers 0l to 3l (dda0l to dda3l) ........................................................ 148 7-5 dma transfer count registers 0 to 3 (dbc0 to dbc3) ........................................................................ 14 9 7-6 dma addressing control registers 0 to 3 (dadc0 to dadc3) ............................................................ 150 7-7 dma channel control registers 0 to 3 (dchc0 to dchc3)................................................................. 152 7-8 dma disable status register (ddis) .......................................................................................... .......... 153 7-9 dma restart register (drst)................................................................................................. .............. 153 7-10 buffer register configuration .............................................................................................. .................. 154 7-11 dmac bus cycle state transition diagram .................................................................................... ...... 157 7-12 single transfer example 1 .................................................................................................. .................. 158 7-13 single transfer example 2 .................................................................................................. .................. 158 7-14 single transfer example 3 .................................................................................................. .................. 159 7-15 single transfer example 4 .................................................................................................. .................. 159 7-16 single-step transfer example 1............................................................................................. ............... 160 7-17 single-step transfer example 2............................................................................................. ............... 160 7-18 line transfer example 1.................................................................................................... .................... 161 7-19 line transfer example 2.................................................................................................... .................... 161 7-20 line transfer example 3.................................................................................................... .................... 162 7-21 line transfer example 4.................................................................................................... .................... 162 7-22 block transfer example..................................................................................................... .................... 163 7-23 one-time transfer when executing single transfers using dmarqn signal..................................... 164 7-24 timing example of terminal count signals (dmtco3 to dmtco0) .................................................... 166 7-25 dma transfer forcible interruption example................................................................................. ........ 167 7-26 dma transfer forcible termination example.................................................................................. ...... 168 7-27 example of two-cycle single transfer timing (between external srams connected to NB85E500). 171 7-28 example of two-cycle single-step transfer timing (between external srams connected to NB85E500)........................................................................... 173 7-29 example of two-cycle line transfer timing (between external srams connected to NB85E500) .... 175 7-30 example of two-cycle block transfer timing (between external srams connected to NB85E500) .. 177
preliminary user?s manual a13971ej7v0um 15 list of figures (3/3) figure no. title page 7-31 example of two-cycle single transfer timing (from ram connected to vdb to sdram connected to nu85e502)....................................................179 7-32 example of two-cycle single transfer timing (from sdram connected to nu85e502 to ram connected to vdb)....................................................181 7-33 example of flyby single transfer timing (from external sram to external i/o connected to NB85E500) ............................................................183 7-34 example of flyby single-step transfer timing (from external sram to external i/o connected to NB85E500) ............................................................185 7-35 example of flyby single-step transfer timing (from external i/o to external sram connected to NB85E500) ............................................................187 7-36 example of flyby line transfer timing (from external sram to external i/o connected to NB85E500) ............................................................189 7-37 example of flyby block transfer timing (from external sram to external i/o connected to NB85E500) ............................................................191 7-38 example of flyby block transfer timing (from external i/o to external sram connected to NB85E500) ............................................................193 8-1 example of non-maskable interrupt request acknowledgment operation............................................200 8-2 non-maskable interrupt processing format.................................................................................... .......202 8-3 reti instruction processing format.......................................................................................... .............203 8-4 maskable interrupt processing format........................................................................................ ...........205 8-5 reti instruction processing format.......................................................................................... .............206 8-6 processing example in which another interrupt request is issued during interrupt servicing .................208 8-7 processing example for simultaneously issued interrupt requests ......................................................210 8-8 interrupt control registers 0 to 63 (pic0 to pic63) ......................................................................... ......211 8-9 interrupt mask registers 0 to 3 (imr0 to imr3) .............................................................................. .......212 8-10 in-service priority register (ispr) ........................................................................................ .................213 8-11 program status word (psw) .................................................................................................. ...............214 8-12 software exception processing format ....................................................................................... ..........215 8-13 reti instruction processing format......................................................................................... ..............216 8-14 illegal opcode ............................................................................................................ ...........................217 8-15 exception trap processing format ........................................................................................... .............218 8-16 example of pipeline operation when interrupt request is acknowledged (outline).............................219 9-1 peripheral macro connection example ......................................................................................... .........223 9-2 user logic design example ................................................................................................... ................225 10-1 NB85E901 and NB85E connection example...................................................................................... ...236 10-2 n-wire type ie connection.................................................................................................. ..................237 10-3 ie connector pin layout diagram (target system side) ....................................................................... 237 10-4 example of recommended circuit for ie connection (NB85E + NB85E901) ........................................239 a-1 rom access timing ................................................................................................................... 240 a-2 ram access timing .................................................................................................................... 241
preliminary user?s manual a13971ej7v0um 16 list of tables table no. title page 2-1 vbttyp1 and vbttyp0 signals ................................................................................................. ........... 29 2-2 vbbenz3 to vbbenz0 signals .................................................................................................. ............ 29 2-3 vbsize1 and vbsize0 signals ................................................................................................. ............. 30 2-4 vbctyp2 to vbctyp0 signals .................................................................................................. ............ 30 2-5 vbseq2 to vbseq0 signals .................................................................................................... .............. 31 2-6 iramwr3 to iramwr0 signals.................................................................................................. ........... 35 2-7 iddrrq, iddwrq, idseq4, and idseq2 signals................................................................................ 37 2-8 ifira64, ifira32, and ifira16 signals ....................................................................................... .......... 40 2-9 ifinsz1 and ifinsz0 signals ................................................................................................. ................ 41 2-10 pin status in each operating mode.......................................................................................... ............... 45 3-1 list of program registers ................................................................................................... ..................... 50 3-2 list of system registers .................................................................................................... ...................... 52 3-3 interrupt/exception table................................................................................................... ...................... 60 3-4 ram area size settings ...................................................................................................... .................... 61 4-1 vbttyp1 and vbttyp0 signals ................................................................................................. ........... 92 4-2 vbctyp2 to vbctyp0 signals .................................................................................................. ............ 92 4-3 vbbenz3 to vbbenz0 signals .................................................................................................. ............ 93 4-4 vbsize1 and vbsize0 signals ................................................................................................. ............. 93 4-5 vbseq2 to vbseq0 signals .................................................................................................... .............. 93 4-6 vbwait, vbahld, and vblast signals .......................................................................................... ..... 94 5-1 setting of setup wait, vpstb wait lengths at each operation frequency ......................................... 120 6-1 operation after halt mode is canceled by interrupt request............................................................. 133 6-2 operation after software stop mode is canceled by interrupt request ............................................. 134 6-3 operation after setting software stop mode in interrupt service routine .......................................... 135 6-4 status after cancellation of hardware stop mode ............................................................................. . 136 7-1 relationships between transfer type and transfer object .................................................................. 144 7-2 relationships between wait function and transfer object .................................................................. 144 8-1 interrupt/exception list .................................................................................................... ...................... 196 9-1 list of test mode settings .................................................................................................. ................... 220 10-1 pin status in each operating mode.......................................................................................... ............. 233 10-2 ie connector pin functions (target system side) ............................................................................ .... 238
preliminary user?s manual a13971ej7v0um 17 chapter 1 introduction the NB85E, which is a cpu core provided for incorporation in an asic, includes an on-chip nec risc 32-bit microprocessor ?v850e1? cpu and various peripheral i/o functions such as a dma controller and interrupt controller. 1.1 outline (1) ?v850e1? cpu the NB85E is equipped with the ?v850e1?, which is a risc type cpu that utilizes a five-stage pipeline technique. two-byte basic instructions and instructions for high-level language support increase the efficiency of object code generated by the c compiler and reduce the program size. in addition, to increase the speed of multiplication processing, the NB85E contains an on-chip high-speed hardware multiplier capable of executing 32-bit 32-bit operations. (2) bus interfaces the NB85E provides the following two types of bus interface for connection with peripheral macros or user logic. ? v850e system bus (vsb) ? nec peripheral i/o bus (npb) the vsb, which is synchronized with the cpu clock, is the bus to be used for connection with high-speed peripheral macros such as a memory controller (memc) or peripheral i/o equipped with an fifo interface. the npb, which operates asynchronously with the cpu clock, is to be used for connection with relatively low- speed peripheral macros such as a timer or asynchronous serial interface (uart). a v850e fetch bus (vfb), which can be directly coupled with rom, and a v850e data bus (vdb), which can be directly coupled with ram, are also provided. in addition, since the NB85E contains on-chip special purpose interfaces for the instruction cache, data cache, and run control unit (rcu), each macro can be directly coupled. (3) on-chip peripheral i/o the NB85E contains an on-chip dma control unit (dmac) for controlling dma transfers, an on-chip interrupt control unit (intc) for controlling interrupt requests, and an on-chip standby control unit (stbc) for controlling the power save function.
chapter 1 introduction preliminary user?s manual a13971ej7v0um 18 1.2 application system the NB85E is incorporated in an asic and connected to memory, user logic, and peripheral macros such as uart and timers. figure 1-1. application system example cpu npb (nec peripheral i/o bus) vsb (v850e system bus) standby control unit (stbc) dma control unit (dmac) test interface control unit (tic) interrupt control unit (intc) bus bridge (bbr) bus control unit (bcu) instruction cache interface data cache interface rcu interface NB85E timer user logic uart memory controller (memc) test bus clock control circuit clock generator (cg) instruction cache rom ram data cache debug controller asic external memory vdb vfb remark vfb: dedicated bus for rom direct coupling (v850e fetch bus) vdb: dedicated bus for ram direct coupling (v850e data bus) caution in this manual, representations related to the memory connected to the NB85E are unified as follows. ? ? ? ? ram: NB85E direct-coupled ram (connected to vdb) ? ? ? ? rom: NB85E direct-coupled rom (connected to vfb) ? ? ? ? external memory: ram or rom connected via the memory controller (memc) (connected via vsb)
chapter 1 introduction preliminary user?s manual a13971ej7v0um 19 1.3 features ? number of instructions 81 ? general-purpose registers 32-bit 32 registers ? instruction set upwardly compatible with v850 cpu signed multiplication (32 bits 32 bits 64 bits) saturated calculation instructions (with overflow/underflow detection function) 32-bit shift instructions: 1 clock bit manipulation instructions load/store instructions with long/short format signed load instructions ? memory space program area: 64 mb linear address space data area: 4 gb linear address space memory bank division function: 2, 4, or 8 mb/bank ? external bus interface vsb (v850e system bus) - address/data separated bus (28-bit address/32-bit data bus) - 32-/16-/8-bit bus sizing function - bus hold function - external wait function - endian switching function npb (nec peripheral i/o bus) - address/data separated bus (14-bit address/16-bit data bus) - programmable wait function - retry function ? interrupt/exception control functions non-maskable interrupts: 3 sources maskable interrupts: 64 sources exceptions: 1 source eight levels of priorities can be set (maskable interrupts) ? dma control function 4-channel configuration transfer units: 8-bit, 16-bit, or 32-bit maximum transfer count: 65536 (2 16 ) transfer types: flyby (1-cycle) transfer or 2-cycle transfer transfer modes: single transfer, single-step transfer, line transfer, or block transfer terminal count output signals (dmtco3 to dmtco0) ? power save function halt mode software stop mode hardware stop mode
chapter 1 introduction preliminary user?s manual a13971ej7v0um 20 ? NB85E901 (rcu note ) interface function note the run control unit (rcu) communicates using jtag and executes debug processing.
chapter 1 introduction preliminary user?s manual a13971ej7v0um 21 1.4 symbol diagram evirel in vaack vareq idmastp in dmarq (3:0) in dmtco (3:0) out dmactv (3:0) out ibdrrq ibea (25:2) ibaack ibdrdy ibdle (3:0) ibedi (31:0) ibbtft iidrrq iiea (25:2) iiaack iidlef iiedi (31:0) iibtft iircan bcunch vptclk out phtest out tesen out tbo (34:0) out cgrel swstoprq hwstoprq dcstopz stprq stpak tbredz out out vpa (13:0) in/out vpd (15:0) out vpwrite out vpstb out out in in vplock vpubenz vpretr vpdact vdselpz vdcsz (7:0) vbseq (2:0) vbctyp (2:0) vbsize (1:0) vbbenz (3:0) vbttyp (1:0) vbd (31:0) in/out in/out in/out in/out in/out in/out in/out in/out in/out in/out in/out in/out in/out in/out out in/out in/out vba (27:0) vbstz vbwrite vblock vbbstr vbwait vblast vbahld vbdc dcresz vbclk test in bunri in out phtdin (1:0) in phtdo (1:0) iroma (19:2) out iromz (31:0) in iromen out iromcs out iromia out iromae out iromwt in irama (27:2) out iramz (31:0) in iramen out iramwr (3:0) out iramrwb out iraoz (31:0) out iramwt in out tmode (1:0) tbi (39:0) in int (63:0) dcnmi (2:0) in in vpresz out iddarq iddrrq iddwrq idaack idseq2 idseq4 irrsa idretr ides iddrdy idrrdy idhum idea (27:0) ided (31:0) idunch out in in out in in out out out out out in in in in/out dbi (5:0) dbo (14:0) dbb (15:0) evastb evdstb evad (15:0) evlkrt evclrip evintak evintrq evintlv (6:0) evien evoen in in in/out out out in/out in in out out ifinsz (1:0) ifirome ifirob2 ifirobe ifiropr ifimode2 ifira16 ifira32 ifira64 ifirase ifirabe ifiuswe ifimaen ifid256 ifiunch (1:0) fcomb pheva ifiwrth ifimode3 in in in in in in in in in in in in in in in in in in in in out in/out out out out out in in in in in in out out out out out out in in in out out out in in in
chapter 1 introduction preliminary user?s manual a13971ej7v0um 22 1.5 function blocks 1.5.1 internal block diagram data cache interface ifinsz1, ifinsz0 ifirome ifirob2 ifirobe ifiropr ifimode2 ifira16 ifira32 ifira64 ifirase ifirabe ifiuswe ifimaen ifid256 ifiunch1, ifiunch0 fcomb pheva dbi5 to dbi0 dbo14 to dbo0 dbb15 to dbb0 ifiwrth evastb evdstb evad15 to evad0 evlkrt evclrip evintak evintrq evintlv6 to evintlv0 evien evoen vpa13 to vpa0 vpd15 to vpd0 vpwrite vpstb vplock vpubenz vpretr vpdact vdselpz vdcsz7 to vdcsz0 vbseq2 to vbseq0 vbctyp2 to vbctyp0 vbsize1, vbsize0 vbbenz3 to vbbenz0 vbttyp1, vbttyp0 vbd31 to vbd0 vaack vareq vba27 to vba0 vbstz vbwrite vblock vbbstr vbwait vblast vbahld vbdc vptclk phtest tesen tbo34 to tbo0 tbredz phtdin1, phtdin0 vpresz tmode1, tmode0 tbi39 to tbi0 ibdrrq ibea25 to ibea2 ibaack ibdrdy ibdle3 to ibdle0 ibedi31 to ibedi0 ibbtft iidrrq iiea25 to iiea2 iiaack iidlef iiedi31 to iiedi0 iibtft iircan bcunch program counter general-purpose registers multiplier (32 32 64) alu barrel shifter cpu v s b iddarq iddrrq iddwrq idaack idseq2 idseq4 irrsa idretr ides iddrdy idrrdy idhum idea27 to idea0 ided31 to ided0 idunch int63 to int0 dcnmi2 to dcnmi0 idmastp dmarq3 to dmarq0 dmtco3 to dmtco0 dmactv3 to dmactv0 dcresz vbclk irama27 to irama2 iramz31 to iramz0 iramen iramwr3 to iramwr0 iramrwb iraoz31 to iraoz0 iramwt test bunri phtdo1, phtdo0 dma control unit (dmac) system controller bus bridge (bbr) ifimode3 instruction queue instruction cache interface bus control unit (bcu) bus arbiter test interface control unit (tic) npb v d b iroma19 to iroma2 iromz31 to iromz0 iromen iromcs iromia iromae iromwt v f b system registers rcu interface cgrel swstoprq hwstoprq dcstopz stprq stpak standby control unit (stbc) evirel interrupt control unit (intc)
chapter 1 introduction preliminary user?s manual a13971ej7v0um 23 1.5.2 internal units (1) cpu the cpu uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic and logic operations, data transfers, and almost all other instruction processing. other dedicated on-chip hardware, such as a hardware multiplier that enables high-speed processing of 32-bit 32-bit multiplication and a barrel shifter, help accelerate the processing of complex instructions. in addition, the cpu has an on-chip rcu interface for connecting to the NB85E901 (rcu) (see chapter 3 cpu ). (2) bcu the bus control unit (bcu), which operates as a bus master on the vsb, controls the on-chip bus bridge (bbr), test interface control unit (tic), and peripheral macros (bus slaves) such as the memory controller (memc) connected to the vsb (see chapter 4 bcu ). (3) bbr the bus bridge (bbr) converts signals for the vsb to signals for the npb. the bbr sets up the wait insertion function and retry function for peripheral macros connected to the npb (see chapter 5 bbr ). (4) stbc the standby control unit (stbc) controls the external clock generator (cg) when the power save function (halt mode, software stop mode, or hardware stop mode) is executed (see chapter 6 stbc ). (5) dmac the dma control unit (dmac) is a four-channel control unit that controls data transfers between memory and peripheral macros or between memory and memory based on dma transfer requests issued by means of the dmarq3 to dmarq0 pins or software triggers (see chapter 7 dmac ). (6) intc the interrupt control unit (intc) processes various types of interrupt requests (see chapter 8 intc ). (7) tic the test interface control unit (tic) is used for test function control. when the tic is set to test mode, test control signals become effective (see chapter 9 test function ). (8) bus arbiter the bus arbiter receives bus control requests from multiple bus masters and arbitrates bus access rights.
preliminary user?s manual a13971ej7v0um 24 chapter 2 pin functions 2.1 list of pin functions (1/4) pin name i/o function vpa13 to vpa0 output address output for peripheral macro connected to npb vpd15 to vpd0 note i/o data input/output for peripheral macro connected to npb vpwrite output write access strobe output of vpd15 to vpd0 signals vpstb output data strobe output of vpd15 to vpd0 signals vplock output bus lock output vpubenz output upper byte enable output vpretr note input retry request input from peripheral macro connected to npb npb pins vpdact input retry function control input vareq input bus access right request input vaack output bus access right acknowledge output vba27 to vba0 note i/o address input/output for peripheral macro connected to vsb vbd31 to vbd0 note i/o data input/output for peripheral macro connected to vsb vbttyp1, vbttyp0 note i/o bus transfer type input/output vbstz note i/o transfer start input/output vbbenz3 to vbbenz0 note i/o byte enable input/output vbsize1, vbsize0 note i/o transfer size input/output vbwrite note i/o read/write status input/output vblock note i/o bus lock input/output vbctyp2 to vbctyp0 note i/o bus cycle status input/output vbseq2 to vbseq0 note i/o sequential status input/output vbbstr note i/o burst read status input/output vbwait note i/o wait response input/output vblast note i/o last response input/output vbahld note i/o address hold response input/output vbdc output data bus direction control output vdcsz7 to vdcsz0 note i/o chip select input/output vsb pins vdselpz note i/o peripheral i/o area access status input/output dcresz input system reset input vbclk input internal system clock input cgrel input clock generator release input swstoprq output software stop mode request output to clock generator hwstoprq output hardware stop mode request output to clock generator system control pins dcstopz input hardware stop mode request input note connected internally to bus holder.
chapter 2 pin functions preliminary user?s manual a13971ej7v0um 25 (2/4) pin name i/o function stprq output hardware/software stop mode request output to memc system control pins stpak input acknowledge input for stprq input of memc idmastp input dma transfer termination input dmarq3 to dmarq0 input dma transfer request input dmtco3 to dmtco0 output terminal count (dma transfer completion) output dmac pins dmactv3 to dmactv0 output dma acknowledge output dcnmi2 to dcnmi0 input non-maskable interrupt request (nmi) input intc pins int63 to int0 input maskable interrupt request input iroma19 to iroma2 output rom address output iromz31 to iromz0 input rom data input iromen output rom access enable output iromwt input rom wait input iromcs output iromia output vfb pins iromae output nec reserved pins (leave open) irama27 to irama2 output ram address output iramz31 to iramz0 input ram data input iraoz31 to iraoz0 output ram data output iramen output ram access enable output iramwr3 to iramwr0 output ram write enable output iramrwb output ram read/write status output vdb pins iramwt input ram wait input ibdrrq input fetch request input from instruction cache ibea25 to ibea2 input fetch address input from instruction cache ibaack output address acknowledge output to instruction cache ibdrdy output data ready output to instruction cache ibdle3 to ibdle0 output data latch enable output to instruction cache ibedi31 to ibedi0 output data output to instruction cache iidrrq output fetch request output to instruction cache iiea25 to iiea2 output fetch address output to instruction cache iiaack input address acknowledge input from instruction cache iidlef input data latch enable input from instruction cache iiedi31 to iiedi0 input data input from instruction cache iibtft output branch target fetch status output to instruction cache iircan output code cancel status output to instruction cache bcunch output uncache status output to instruction cache instruction cache pins ibbtft input nec reserved pin (input low level)
chapter 2 pin functions preliminary user?s manual a13971ej7v0um 26 (3/4) pin name i/o function iddarq output read/write access request output to data cache idaack output acknowledge output iddrrq input vsb read operation request input to bcu iddwrq input vsb write operation request input to bcu idseq4 input read/write operation type setting input idseq2 input read/write operation type setting input irrsa output vdb hold status output idretr output read retry request output idunch output uncache status output iddrdy output read data ready output idrrdy input read data ready input from data cache idhum input hit under miss-hit read input idea27 to idea0 input address input ided31 to ided0 note 1 i/o data input/output data cache pins ides output nec reserved pin note 2 dbi5 to dbi0 input debug control input dbo14 to dbo0 output debug control output rcu pins dbb15 to dbb0 note 1 i/o debug control input/output evastb input address strobe input evdstb input data strobe input evad15 to evad0 note 1 i/o address/data input/output evien output evadn input enable output (n = 15 to 0) evoen output evadn output enable output (n = 15 to 0) evlkrt note 1 i/o lock/retry input/output evirel input standby release input evclrip input ispr clear input evintak input interrupt acknowledge input evintrq output interrupt request output peripheral evaluation chip mode pins evintlv6 to evintlv0 output interrupt vector output ifirome input rom mapping enable input ifirob2 input rom area location setting input ifira64 input ram area size selection input ifira32 input ram area size selection input ifira16 input ram area size selection input ifimaen input misalign access setting input operation mode setting pins ifid256 input data area setting input notes 1. connected internally to bus holder. 2. when using the data cache, always connect this pin to the ides pin of the data cache. leave open when unused.
chapter 2 pin functions preliminary user?s manual a13971ej7v0um 27 (4/4) pin name i/o function ifinsz1, ifinsz0 input vsb data bus size (initial value) selection input ifiwrth input data cache write-back/write-through mode selection input ifiunch1 input data cache setting input ifiunch0 input instruction cache setting input pheva input peripheral evaluation chip mode setting input ifirobe input ifiropr input ifirase input ifirabe input ifimode3 input ifimode2 input ifiuswe input operation mode setting pins fcomb input nec reserved pins (input low level) tbi39 to tbi0 input input test bus tbo34 to tbo0 output output test bus test input test bus control input bunri input normal/test mode selection input phtdo1, phtdo0 note input peripheral macro test input tesen output peripheral macro test enable output vptclk output peripheral macro test clock output phtdin1, phtdin0 output peripheral macro test output vpresz output peripheral macro reset output phtest output peripheral test mode status output tmode1 output test mode selection output tmode0 output test mode pins tbredz output nec reserved pins (leave open) note connected internally to bus holder.
chapter 2 pin functions preliminary user?s manual a13971ej7v0um 28 2.2 explanation of pin functions 2.2.1 npb pins (1) vpa13 to vpa0 (output) these are pins from which addresses are output to peripheral macros connected to the npb. they specify the lower 14 bits. (2) vpd15 to vpd0 (input/output) these are pins to/from which data is input to/output from peripheral macros connected to the npb. (3) vpwrite (output) this is the write access strobe output pin for the vpd15 to vpd0 signals. during writing, a high level is output. (4) vpstb (output) this is the data strobe output pin for the vpd15 to vpd0 signals. (5) vplock (output) this is the bus lock output pin. if an interrupt request occurs while a read modify write access to the interrupt control register (picn) is executed, this pin outputs a bus lock signal to avoid loss of the interrupt request. it outputs a high level during a read modify write access. even when an interrupt request occurs, transfer to the pifn flag of the picn register is not performed while this signal outputs a high level (n = 0 to 63). (6) vpubenz (output) this is the higher byte enable output pin. it outputs a low level during a halfword data access or a byte data access to an odd address. it outputs a high level during a byte access to an even address. (7) vpretr (input) this is the pin to which retry requests are input from peripheral macros connected to the npb. if a high level is input to this pin and to the vpdact pin at the falling edge of the vpstb signal, the read/write operation is performed again. (8) vpdact (input) this pin, which is an input pin for input from an external address decoder, is used to enable the retry function. when a high level is input, the retry function is enabled. when a low level is input, any retry request by vpretr input will be ignored. 2.2.2 vsb pins (1) vareq (input) this is the pin to which bus access right requests are input from an external bus master. (2) vaack (output) this is an output pin for indicating that the bus access right request signal (vareq) from an external bus master has been acknowledged.
chapter 2 pin functions preliminary user?s manual a13971ej7v0um 29 (3) vba27 to vba0 (input/output) these pins constitute an address bus for peripheral macros connected to the vsb. the bus master having the bus access right outputs signals from these pins. (4) vbd31 to vbd0 (input/output) these pins constitute a data bus for peripheral macros connected to the vsb. during writing, the bus master having the bus access right outputs signals from these pins. during reading, the selected bus slave outputs signals from these pins. (5) vbttyp1, vbttyp0 (input/output) these pins indicate the bus transfer type. while the vbclk signal is high level, the bus master having the bus access right outputs signals from these pins. table 2-1. vbttyp1 and vbttyp0 signals vbttyp1 vbttyp0 transfer type l l address-only transfer (transfer with no data processing) h l non-sequential transfer (single transfer or burst transfer) h h sequential transfer (transfer in which the address that is currently being transferred is related to the address for the previous transfer) l h (reserved for future function expansion) remark l: low-level h: high-level (6) vbstz (input/output) this pin indicates the transfer start. the bus master having the bus access right outputs a signal from this pin. (7) vbbenz3 to vbbenz0 (input/output) these are low-level active pins that indicate the enabled byte data among the data bus pins (vbd31 to vbd0). the bus master having the bus access right outputs signals from these pins. table 2-2. vbbenz3 to vbbenz0 signals active (low-level output) signal enabled byte data vbbenz0 vbd7 to vbd0 vbbenz1 vbd15 to vbd8 vbbenz2 vbd23 to vbd16 vbbenz3 vbd31 to vbd24 (8) vbsize1, vbsize0 (input/output) these pins indicate the transfer size. the bus master having the bus access right outputs signals from these pins.
chapter 2 pin functions preliminary user?s manual a13971ej7v0um 30 table 2-3. vbsize1 and vbsize0 signals vbsize1 vbsize0 transfer size l l byte (8 bits) l h halfword (16 bits) h l word (32 bits) h h (reserved for future function expansion) remark l: low-level h: high-level (9) vbwrite (input/output) this pin indicates read or write. the bus master having the bus access right outputs a signal from this pin. during writing, a high level is output. (10) vblock (input/output) this pin is used to retain the bus access right. the bus master having the bus access right outputs a signal from this pin. this pin is used to inhibit interruption due to an access from another bus master between the current transfer and the next transfer. (11) vbctyp2 to vbctyp0 (input/output) these pins are used to indicate the current bus cycle status. the bus master having the bus access right outputs signals from these pins. table 2-4. vbctyp2 to vbctyp0 signals vbctyp2 vbctyp1 vbctyp0 bus cycle status lllopc ode fetch l l h data access lhl misalign access note l h h read modify write access h l l opcode fetch of jump address due to branch instruction h h l dma 2-cycle transfer hhhdma flyby transfer h l h (reserved for future function expansion) note only output when a high level is input to the ifimaen pin (misalign access enabled). remark l: low-level h: high-level (12) vbseq2 to vbseq0 (input/output) these are sequential status pins. during a burst transfer, the bus master having the bus access right outputs signals from these pins to indicate the transfer size. when a burst transfer starts, these pins indicate the ?burst transfer length?. during the burst transfer, they indicate ?continuous?. at the end of the burst transfer, they indicate ?single transfer?.
chapter 2 pin functions preliminary user?s manual a13971ej7v0um 31 in the following cases, vsb is in the burst transfer mode and the sequential status is ?continuous?. ? when 16-/32-bit data is transferred with a vsb width of 8 bits. ? when 32-bit data is transferred with a vsb width of 16 bits. ? when a refill is being performed from the instruction/data cache. ? when 32-bit data is transferred to the peripheral macro connected to the npb (16-bit data bus width). table 2-5. vbseq2 to vbseq0 signals vbseq2 vbseq1 vbseq0 sequential status lllsingle transfer l l h continuous (indicates that the next transfer address is related to the current transfer address) note l h l continuous 4 times (burst transfer length: 4) l h h continuous 8 times (burst transfer length: 8) h l l continuous 16 times (burst transfer length: 16) h l h continuous 32 times (burst transfer length: 32) h h l continuous 64 times (burst transfer length: 64) hhhconti nuous 128 times (burst transfer length: 128) note this is output for continuous 2 times and throughout continuous 4, 8, 16, 32, 64, and 128 times. remark l: low-level h: high-level (13) vbbstr (input/output) this is the burst read status pin. when the connected rom (accessed via vsb) is used as external memory, the bus master having the bus access right outputs a signal from this pin to indicate that the current transfer is an opcode fetch from external rom. this pin operates with the same timing as the address bus. (14) vbwait (input/output) this is the wait response signal i/o pin. if further bus cycles are to be requested because the data is not yet ready, this signal is output from the selected bus slave to the bus master. when this signal becomes high level, the bus cycle shifts to the wait state. note that when a memory controller (memc) is connected to the NB85E, because the access cycle will be at least two clocks, a high level will be output from the memc to the NB85E while the vsb cycle is being generated. (15) vblast (input/output) this is the last response signal i/o pin. this is used when the bus decoder needs decode cycles. if there are multiple bus slaves connected externally and a decoder has been added for slave selection, decoding for bus slave selection is normally performed during non-sequential transfer. for that reason, decode cycles for slave selection cannot be issued when trying to change a slave device during sequential transfer, such as during burst transfer. in this case, the slave device outputs the last response and notifies the bus master that the slave signal will change. when there is a last response from the slave device, the bus master makes the next bus cycle a non- sequential transfer enabling decode cycle issuance.
chapter 2 pin functions preliminary user?s manual a13971ej7v0um 32 (16) vbahld (input/output) this is the address hold response signal i/o pin. to request further bus cycles when the selected bus slave has completed the preparations for data output, this signal is output to the bus master. when this signal and the vbwait signal become high level, the bus cycle shifts to the address hold state. in the address hold state, the circuit configuration can be simplified because no address latch is necessary since the address for the data does not change during its read/write cycle. note that when a memory controller (memc) is connected to the NB85E, a high level is output to the NB85E from the memc when an idle state is inserted. (17) vbdc (output) this is the data bus direction control output pin. during reading, a high level is output. this pin is connected to the 3-state buffer enable pin to control the data bus direction. (18) vdcsz7 to vdcsz0 (input/output) these are chip select pins. for details, see 4.3 programmable chip select function . (19) vdselpz (input/output) when the peripheral i/o area and programmable peripheral i/o area are accessed, the bus master outputs a low level from this pin. 2.2.3 system control pins (1) dcresz (input) this is the clock-synchronized system reset input pin. when the stable input clock rising edge is detected five times after a low level was input to this pin, the pin statuses and internal signals are completely initialized. also, when the input clock rising edge is detected four times after this signal has risen from low level to high level, the pipeline is cleared and program execution starts from memory address 0. in addition to normal initialization and start operations, this pin is used to cancel the power save function. caution be sure to input the dcresz signal so that the setup and hold times referenced to the vbclk signal are satisfied. figure 2-1. acknowledgement of dcresz signal note input at least five clocks of the vbclk signal while the dcresz signal is low level. always input a stable clock to the vbclk pin. vbclk (input) dcresz (input) internal system reset signal note completion of initialization start of program execution completion of initialization start of program execution note
chapter 2 pin functions preliminary user?s manual a13971ej7v0um 33 (2) vbclk (input) this is the external clock input pin for the internal system clock. a 50% duty stable clock is input from an external clock control circuit. (3) cgrel (input) this is the release input pin for the external clock generator (cg). an active level (high level) is input upon the start of vbclk input at least one clock after stop mode is canceled and the oscillation stabilization time has been ensured (it is not necessary to set cgrel input at the same time as vbclk input). (4) swstoprq (output) this is the pin from which software stop mode requests are output to the external clock generator (cg). when software stop mode is set, this pin outputs a high-level signal. vbclk input from the cg is stopped by using this signal. when software stop mode is canceled, this pin outputs a low-level signal. (5) hwstoprq (output) this is the pin from which hardware stop mode requests are output to the external clock generator (cg). when hardware stop mode is set by dcstopz input, this pin outputs a high-level signal. vbclk input from the cg is stopped by using this signal. when hardware stop mode is canceled, this pin outputs a low-level signal. (6) dcstopz (input) this is a hardware stop mode request input pin. when a low-level signal is input, the NB85E is set to hardware stop mode. (7) stprq (output) this is the pin from which hardware/software stop mode requests are output to the memory controller (memc). (8) stpak (input) this is the pin to which acknowledge signals are input from the memory controller (memc) acknowledging the stprq signal. 2.2.4 dmac pins (1) idmastp (input) this is the dma transfer forcible interrupt input pin. input an active level (high level) of two clocks in synchronization with the rising edge of the vbclk signal. to restart transfer, set (1) the en bit of the drst register after inputting a low level to this pin. (2) dmarq3 to dmarq0 (input) these are the dma transfer request input pins. input an active level (high level) in synchronization with the rising edge of the vbclk signal, and continue inputting until the corresponding dmactvn signal becomes high level (n = 3 to 0). (3) dmtco3 to dmtco0 (output) these are the terminal count (dma transfer completion) output pins. a one-clock high level is output from these pins when the final dma transfer is performed. the high level is output in synchronization with the rising edge of the vbclk signal.
chapter 2 pin functions preliminary user?s manual a13971ej7v0um 34 (4) dmactv3 to dmactv0 (output) these are the dma acknowledge output pins. these pins become active (high-level output) during a 2-cycle transfer vsb read or vsb write cycle, or during a flyby transfer. 2.2.5 intc pins (1) dcnmi2 to dcnmi0 (input) these are the non-maskable interrupt request (nmi) input pins. when a rising edge is input, a non-maskable interrupt is generated. (2) int63 to int0 (input) these are the maskable interrupt request input pins. when a rising edge is input, a maskable interrupt is generated. 2.2.6 vfb pins (1) iroma19 to iroma2 (output) these pins constitute a bus from which addresses are output to rom. (2) iromz31 to iromz0 (input) these pins constitute a bus to which data is input from rom. (3) iromen (output) this is the pin from which access enable signals are output to rom. it changes in synchronization with the falling edge of the vbclk signal. (4) iromwt (input) this is the pin to which wait signals are input from rom. a high level is input during the wait period. (5) iromcs, iromia, iromae (output) these are nec reserved pins. leave them open. 2.2.7 vdb pins (1) irama27 to irama2 (output) these pins constitute a bus from which addresses are output to ram. the irama27 to irama16 signals are output for the data cache. therefore, they do not have to be decoded when ram is connected. (2) iramz31 to iramz0 (input) these pins constitute a bus to which data is input from ram. (3) iraoz31 to iraoz0 (output) these pins constitute a bus from which data is output to ram. (4) iramen (output) this is the pin from which access enable signals are output to ram. it changes in synchronization with the falling edge of the vbclk signal.
chapter 2 pin functions preliminary user?s manual a13971ej7v0um 35 (5) iramwr3 to iramwr0 (output) these are the pins from which write enable signals are output to ram. they are high-level active pins that indicate the enabled byte data among the output data bus pins (iraoz31 to iraoz0). table 2-6. iramwr3 to iramwr0 signals active signal enabled byte data iramwr0 iraoz7 to iraoz0 iramwr1 iraoz15 to iraoz8 iramwr2 iraoz23 to iraoz16 iramwr3 iraoz31 to iraoz24 (6) iramrwb (output) this is the pin from which the read/write status is output to ram. during reading, a high-level signal is output. during writing, a low-level signal is output. (7) iramwt (input) this is the pin to which wait signals are input from the data cache. a high level is input during the wait period. 2.2.8 instruction cache pins (1) ibdrrq (input) this is the pin to which fetch requests are input from the instruction cache. a request signal is input which fetches data from the external memory to the NB85E. (2) ibea25 to ibea2 (input) these pins constitute a bus to which fetch addresses are input from the instruction cache. upon a miss-hit, the address to be read is input from the instruction cache. (3) ibaack (output) this is the pin from which address acknowledgements are output to the instruction cache. this signal is output when the NB85E recognizes the ibea25 to ibea2 signals input from the instruction cache. (4) ibdrdy (output) this is the pin from which data ready signals are output to the instruction cache. upon an instruction cache miss-hit, when the NB85E has finished fetching the data to be read from the external memory, this signal is output to indicate that a refill for the instruction cache is ready. (5) ibdle3 to ibdle0 (output) these are the pins from which data latch enable signals are output to the instruction cache. (6) ibedi31 to ibedi0 (output) these pins constitute a bus from which data is output to the instruction cache. upon an instruction cache miss-hit, the data to be refilled is output to the instruction cache. (7) iidrrq (output) this is the pin from which fetch requests are output to the instruction cache.
chapter 2 pin functions preliminary user?s manual a13971ej7v0um 36 (8) iiea25 to iiea2 (output) these pins constitute a bus from which fetch addresses are output to the instruction cache. the address to be fetched is output from the external memory simultaneous with the fetch request (iidrrq). (9) iiaack (input) this is the pin to which address acknowledgements are input from the instruction cache. this signal is input to the NB85E when the instruction cache recognizes the fetch address signals (iiea25 to iiea2) input from the NB85E. (10) iidlef (input) this is the pin to which data latch enable signals are input from the instruction cache. (11) iiedi31 to iiedi0 (input) these pins constitute a bus to which data is input from the instruction cache. the data to be read is input from the instruction cache. (12) iibtft (output) this is the pin from which the branch target fetch status is output to the instruction cache. a high level is output when a jump destination address is fetched due to a branch instruction. (13) iircan (output) this is the pin from which the code cancel status is output to the instruction cache. this signal cancels previous requests when data becomes unwanted due to a branch or interrupt after the NB85E outputs a fetch request to the instruction cache. (14) bcunch (output) this is the pin from which the uncache status is output to the instruction cache. a low level is output when the area in which the instruction cache setting has been set to cache-enable using the cache configuration register (bhc) is accessed. (15) ibbtft (input) this is an nec reserved pin. always input a low level. note that the ibbtft pin of the connected instruction cache should be left open when using the instruction cache. 2.2.9 data cache pins (1) iddarq (output) this is the pin from which read/write access requests are output to the data cache. (2) idaack (output) this is the pin from which acknowledgements are output to the data cache. this signal is output when the NB85E recognizes the idea27 to idea0 signals input from the data cache. (3) iddrrq, iddwrq, idseq4, idseq2 (input) these are the pins to which the operation type settings are input from the data cache.
chapter 2 pin functions preliminary user?s manual a13971ej7v0um 37 table 2-7. iddrrq, iddwrq, idseq4, and idseq2 signals iddrrq iddwrq idseq4 idseq2 operation type h l h l 4-word sequential read h l l h 2-word sequential read h l l l 1-word read l h h l 4-word sequential write l h l h 2-word sequential write lhll1-word write hhhh1-word write h h h l 1-halfword write h h l l 1-byte write other than above setting prohibited remark l: low-level input h: high-level input (a) iddrrq (input) this is the pin to which vsb read operation requests are input from the data cache. (b) iddwrq (input) this is the pin to which vsb write operation requests are input from the data cache. (c) idseq4, idseq2 (input) these are the pins to which the read/write operation type settings are input from the data cache. (4) irrsa (output) this is the pin from which the vdb hold status is output to the data cache. an active level (high level) is output when the vdb is accessing ram or is in the hold state. (5) idretr (output) this is the pin from which read retry requests are output to the data cache. (6) idunch (output) this is the pin from which the uncache status is output to the data cache. a low level is output when the area in which the data cache setting has been set to cache-enable using the cache configuration register (bhc) is accessed. (7) iddrdy (output) this is the pin from which read data ready signals are output to the data cache. upon a data cache miss-hit, when the NB85E has finished fetching the data to be read from the external memory, this signal is output to indicate that a refill for the data cache is ready. (8) idrrdy (input) this is the pin to which read data ready signals are input from the data cache.
chapter 2 pin functions preliminary user?s manual a13971ej7v0um 38 (9) idhum (input) this is the pin to which hit-under-miss-hit read signals are input from the data cache. a high level is input in cases when a subsequent access is made to the data cache while the external memory is being accessed due to the generation of a miss-hit during a read operation, and the data that scored a hit on this subsequent access is input to the NB85E ahead of the data from the external memory (hit-under-miss-hit). (10) idea27 to idea0 (input) these pins constitute a bus to which addresses are input from the data cache. the address to be accessed is input to the NB85E upon a data cache miss-hit. (11) ided31 to ided0 (input/output) these pins constitute a data bus through which data is input/output from/to the data cache. data for refilling the data cache and data written to the external memory in write back mode is exchanged. (12) ides (output) this is an nec reserved pin. when using the data cache, be sure to connect this pin to the ides pin of the connected data cache. when not using the data cache, leave this pin open. 2.2.10 rcu pins (1) dbi5 to dbi0 (input) these are debug control input pins. they are connected to the dbi5 to dbi0 pins of the rcu. (2) dbo14 to dbo0 (output) these are debug control output pins. they are connected to the dbo14 to dbo0 pins of the rcu. (3) dbb15 to dbb0 (input/output) these are debug control i/o pins. they are connected to the dbb15 to dbb0 pins of the rcu. 2.2.11 peripheral evaluation chip mode pins if a high-level signal is input to the pheva pin, the NB85E is set to peripheral evaluation chip mode. in peripheral evaluation chip mode, the asic in which the NB85E is incorporated is used as a peripheral emulation chip when the in-circuit emulator is used to perform debugging. the peripheral evaluation chip mode pins constitute an interface with the evaluation chip within the in-circuit emulator, and various evaluation chip signals are converted to npb signals via these pins. (1) evastb (input) this is the address strobe input pin. it is connected to the ephastb pin of the evaluation chip. (2) evdstb (input) this is the data strobe input pin. it is connected to the ephdstb pin of the evaluation chip. (3) evad15 to evad0 (input/output) these pins constitute an address/data bus. they are connected to the ephadn pins of the evaluation chip (n = 15 to 0).
chapter 2 pin functions preliminary user?s manual a13971ej7v0um 39 (4) evien (output) this pin outputs an input enable signal for controlling the direction of the i/o buffer on the evadn bus (n = 15 to 0). (5) evoen (output) this pin outputs an output enable signal for controlling the direction of the i/o buffer on the evadn bus (n = 15 to 0). (6) evlkrt (input/output) this is the lock/retry input/output pin. it is connected to the ephlkrt pin of the evaluation chip. (7) evirel (input) this is the standby release input pin. (8) evclrip (input) this is the ispr clear input pin. it is connected to the eclrip pin of the evaluation chip. (9) evintak (input) this is the interrupt acknowledge input pin. it is connected to the eintak pin of the evaluation chip. (10) evintrq (output) this is the interrupt request output pin. it is connected to the eintrq pin of the evaluation chip. (11) evintlv6 to evintlv0 (output) these are the interrupt vector output pins. they are connected to the eintlv6 to eintlv0 pins of the evaluation chip. 2.2.12 operation mode setting pins the following pins are used to specify the operation mode of the NB85E. the input level to these pins should remain fixed during NB85E operation. do not change the input level to these pins during operation. (1) ifirome (input) this is the rom area setting input pin. the setting is made according to the level input to the pin, as shown below. ? low level: rom connected as external memory (via vsb) is used ? high level: rom connected to vfb is used when a low level is input to this pin, instruction processing begins after branching to the reset entry address of the external memory, following the release of system reset. instruction fetches and data access to the rom connected to vfb cannot be performed. if a high level is input to this pin and a low level is input to the ifirob2 pin, instruction processing begins after branching to the reset entry address of the rom connected to vfb, following the release of system reset. if a high level is input to the ifirob2 pin, instruction processing begins after branching to the reset entry address of the external memory, following the release of system reset, however it is possible to access the area of rom connected to vfb that is allocated to addresses 100000h and higher.
chapter 2 pin functions preliminary user?s manual a13971ej7v0um 40 (2) ifirob2 (input) this is the rom area relocation setting input pin. it specifies the range for locating the rom area. the rom area range is set as follows according to the input level to this pin. ? low level: addresses 000000h to 0fffffh ? high level: addresses 100000h to 1fffffh for details, see 3.4.1 (1) rom relocation function . (3) ifira64, ifira32, ifira16 (input) these are ram area size selection input pins. the ram area size is set as follows according to the input level to these pins. for details, see 3.4.2 ram area . table 2-8. ifira64, ifira32, and ifira16 signals ifira64 ifira32 ifira16 ram area size lll4 kb l l h 12 kb l h arbitrary 28 kb h arbitrary arbitrary 60 kb remark l: low-level input h: high-level input (4) ifimaen (input) this is the misalign access setting input pin. misalign access is enabled or disabled as follows according to the input level to this pin. ? low level: misalign access disabled ? high level: misalign access enabled (5) ifid256 (input) this is the data area setting input pin. it is used to set the data area size. each mode is set as follows according to the input level to this pin. for details, see 3.3.2 data area . ? low level: 64 mb mode ? high level: 256 mb mode (6) ifinsz1, ifinsz0 (input) these are the vsb data bus size (initial value) selection input pins. the vsb data bus size is set as follows according to the input level to these pins.
chapter 2 pin functions preliminary user?s manual a13971ej7v0um 41 table 2-9. ifinsz1 and ifinsz0 signals ifinsz1 ifinsz0 vsb data bus size l l 32 bits l h 16 bits h l 8 bits h h setting prohibited remark l: low-level input h: high-level input if the vsb data bus size is changed after reset through the bus size configuration register (bsc), the setting of the bsc register is valid regardless of the input level to these pins. (7) ifiwrth (input) this is the data cache write-back or write-through mode selection input pin. when using the data cache, connect to the ifiwrth pin of the data cache. each mode is set as follows according to the input level to this pin. ? low level: write-back mode ? high level: write-through mode (8) ifiunch1 (input) this is the data cache setting input pin. when using the data cache, connect to the ifiunch1 pin of the data cache. the data cache is enabled or disabled as follows according to the input level to this pin. ? low level: data cache is enabled ? high level: data cache is disabled (9) ifiunch0 (input) this is the instruction cache setting input pin. the instruction cache is enabled or disabled as follows according to the input level to this pin. ? low level: instruction cache is enabled ? high level: instruction cache is disabled (10) pheva (input) this is the peripheral evaluation chip mode setting input pin. a high level is input when the asic in which the NB85E has been incorporated is used as a peripheral evaluation chip. (11) ifirobe, ifiropr, ifirase, ifirabe, ifimode3, ifimode2, ifiuswe, fcomb (input) these are nec reserved pins. always input low-level signals.
chapter 2 pin functions preliminary user?s manual a13971ej7v0um 42 2.2.13 test mode pins for details about the tbi39 to tbi0, tbo34 to tbo0, test, and bunri pins, refer to the various cell-based ic family design manuals. (1) tbi39 to tbi0 (input) these pins constitute an input test bus. (2) tbo34 to tbo0 (output) these pins constitute an output test bus. (3) test (input) this is the test bus control input pin. (4) bunri (input) this is the input pin for selecting normal or test mode. (5) phtdo1, phtdo0 (input) these pins are the peripheral macro test input pins. (6) tesen (output) this is the enable output pin for setting peripheral macros to test mode. (7) vptclk (output) this is the clock output pin for peripheral macro tests. (8) phtdin1, phtdin0 (output) these are the peripheral macro test output pins. (9) vpresz (output) this is the pin from which reset signals are output to the peripheral macros. caution the vpresz signal is the reset signal for the peripheral macros in normal operation mode as well as test mode. (10) phtest (output) this is the pin from which signals indicating the peripheral test mode status are output. (11) tmode1 (output) this is the test mode selection output pin. when using the rcu, connect this pin to the tmode1 pin of the rcu. (12) tmode0, tbredz (output) these are nec reserved pins. leave them open.
chapter 2 pin functions preliminary user?s manual a13971ej7v0um 43 2.3 recommended connection of unused pins (1/2) pin name i/o recommended connection method vpa13 to vpa0, vpwrite, vpstb, vplock, vpubenz output leave open. vpd15 to vpd0 i/o leave open. vpretr input input low level. npb pins vpdact input input high level. vbwait, vblast, vbahld i/o note vareq input input low level. vaack, vbdc output leave open. vsb pins vba27 to vba0, vbd31 to vbd0, vbttyp1, vbttyp0, vbstz, vbbenz3 to vbbenz0, vbsize1, vbsize0, vbwrite, vblock, vbctyp2 to vbctyp0, vbseq2 to vbseq0, vbbstr, vdcsz7 to vdcsz0, vdselpz i/o leave open. dcresz, vbclk input ? cgrel input input low level. swstoprq, hwstoprq, stprq output leave open. system control pins dcstopz, stpak input input high level. idmastp, dmarq3 to dmarq0 input input low level. dmac pins dmtco3 to dmtco0, dmactv3 to dmactv0 output leave open. intc pins dcnmi2 to dcnmi0, int63 to int0 input input low level. iroma19 to iroma2, iromen, iromcs, iromia, iromae output leave open. iromz31 to iromz0 input input high level. vfb pins iromwt input input low level. irama27 to irama2, iraoz31 to iraoz0, iramen, iramwr3 to iramwr0, iramrwb output leave open. iramz31 to iramz0 input input high level. vdb pins iramwt input input low level. ibdrrq, ibea25 to ibea2, iiaack, iidlef, iiedi31 to iiedi0, ibbtft input input low level. instruction cache pins ibaack, ibdrdy, ibdle3 to ibdle0, ibedi31 to ibedi0, iidrrq, iiea25 to iiea2, iibtft, iircan, bcunch output leave open. iddarq, idaack, irrsa, idretr, idunch, iddrdy, ides output leave open. iddrrq, iddwrq, idseq4, idseq2, idrrdy, idhum, idea27 to idea0 input input low level. data cache pins ided31 to ided0 i/o leave open. note the recommended connections of the vbwait, vblast, and vbahld pins differ as follows. ? when none of above three pins are used: leave open. ? when one or more of above three pins are used: input a low level.
chapter 2 pin functions preliminary user?s manual a13971ej7v0um 44 (2/2) pin name i/o recommended connection method dbi5, dbi1 input input high level. dbi4 to dbi2, dbi0 input input low level. dbo14 to dbo0 output leave open. rcu pins dbb15 to dbb0 i/o leave open. evastb, evdstb, evirel, evclrip, evintak input input low level. evad15 to evad0, evlkrt i/o leave open. peripheral evaluation chip mode pins evien, evoen, evintrq, evintlv6 to evintlv0 output leave open. ifirome, ifira64, ifira32, ifira16, ifimaen, ifid256, ifinsz1, ifinsz0 input ? ifiunch1 input input high level. ifirob2, ifiwrth, ifiunch0 input input low level or high level. operation mode setting pins pheva, ifirobe, ifiropr, ifirase, ifirabe, ifimode3, ifimode2, ifiuswe, fcomb input input low level. tbi39 to tbi0 input tbo34 to tbo0 output refer to the design editions of the various cell- based ic family user?s manuals. test, bunri input ? phtdo1, phtdo0 input input low level. test mode pins tesen, vptclk, phtdin1, phtdin0, vpresz, phtest, tmode1, tmode0, tbredz output leave open.
chapter 2 pin functions preliminary user?s manual a13971ej7v0um 45 2.4 pin status the following table shows the status in each operating mode of the pins that have output functions. table 2-10. pin status in each operating mode (1/3) pin name pin status reset note software stop mode hardware stop mode halt mode standby test mode unit test mode vpa13 to vpa0 undefined retained retained operates undefined operates vpwrite undefined retained retained operates undefined operates vpstb l l l operates undefined operates vplock undefined retained retained operates undefined operates vpubenz undefined retained retained operates undefined operates npb pins vpd15 to vpd0 undefined retained retained operates undefined operates vaack l retained retained operates undefined operates vbdc l l l operates undefined operates vba27 to vba0 undefined retained retained operates undefined operates vbd31 to vbd0 undefined retained retained operates undefined operates vbttyp1, vbttyp0 l retained retained operates undefined operates vbstz h retained retained operates undefined operates vbbenz3 to vbbenz0 h retained retained operates undefined operates vbsize1, vbsize0 undefined retained retained operates undefined operates vbwrite l retained retained operates undefined operates vblock l retained retained operates undefined operates vbctyp2 to vbctyp0 undefined retained retained operates undefined operates vbseq2 to vbseq0 undefined retained retained operates undefined operates vbbstr l retained retained operates undefined operates vbwait l retained retained operates undefined operates vblast l retained retained operates undefined operates vbahld l retained retained operates undefined operates vdcsz7 to vdcsz0 h retained retained operates undefined operates vsb pins vdselpz h retained retained operates undefined operates note when a low level is input to the dcresz pin and an external clock is input to the vbclk pin. remark l: low-level output h: high-level output retained: retains status in external bus cycle immediately before
chapter 2 pin functions preliminary user?s manual a13971ej7v0um 46 table 2-10. pin status in each operating mode (2/3) pin name pin status reset note software stop mode hardware stop mode halt mode standby test mode unit test mode swstoprq l h l l undefined undefined hwstoprq l l h l undefined undefined system control pins stprq l h h l undefined undefined dmtco3 to dmtco0 l l l operates undefined undefined dmac pins dmactv3 to dmactv0 l l l operates undefined undefined iroma19 to iroma2 undefined retained retained retained undefined operates iromen l l l l undefined operates iromcs l l l l undefined operates iromia h undefined undefined undefined undefined operates vfb pins iromae undefined undefined undefined undefined undefined operates irama27 to irama2 undefined undefined undefined operates undefined operates iraoz31 to iraoz0 undefined undefined undefined operates undefined operates iramen l l l operates undefined operates iramwr3 to iramwr0 l l l operates undefined operates vdb pins iramrwb undefined undefined undefined operates undefined operates ibaack l l l l undefined operates ibdrdy l l l l undefined operates ibdle3 to ibdle0 l l l l undefined operates ibedi31 to ibedi0 undefined undefined undefined undefined undefined operates iidrrq l l l l undefined operates iiea25 to iiea2 undefined undefined undefined undefined undefined operates iibtft undefined undefined undefined undefined undefined operates iircan undefined undefined undefined undefined undefined operates instruction cache pins bcunch l l l l undefined operates iddarq l l l l undefined operates data cache pins idaack l l l l undefined operates note when a low level is input to the dcresz pin and an external clock is input to the vbclk pin. remark l: low-level output h: high-level output retained: retains status in external bus cycle immediately before
chapter 2 pin functions preliminary user?s manual a13971ej7v0um 47 table 2-10. pin status in each operating mode (3/3) pin name pin status reset note software stop mode hardware stop mode halt mode standby test mode unit test mode irrsa l undefined undefined undefined undefined operates idretr l l l l undefined operates idunch undefined undefined undefined undefined undefined operates iddrdy l l l l undefined operates ided31 to ided0 undefined undefined undefined undefined undefined operates data cache pins ides undefined undefined undefined undefined undefined operates dbo14 h l l l undefined undefined dbo13 l l l l undefined undefined dbo12 to dbo5 retained retained retained retained undefined undefined dbo4 l l l h undefined undefined dbo3 to dbo1 l l l l undefined undefined dbo0 l retained retained retained undefined undefined rcu pins dbb15 to dbb0 undefined retained retained retained undefined undefined evien undefined l l l undefined undefined evoen undefined l l l undefined undefined evintrq l retained retained operates undefined undefined evintlv6 to evintlv0 undefined retained retained operates undefined undefined evad15 to evad0 undefined retained retained undefined undefined undefined peripheral evaluation chip mode pins evlkrt undefined retained retained undefined undefined undefined tbo34 to tbo0 hi-z hi-z hi-z hi-z hi-z operates tesen l l l l l operates vptclk l l l l l operates phtdin1, phtdin0 l l l l l operates vpresz l h h h undefined undefined phtest l l l l l operates tmode1, tmode0 l l l l l operates test mode pins tbredz h h h h h operates note when a low level is input to the dcresz pin and an external clock is input to the vbclk pin. remark l: low-level output h: high-level output retained: retains status in external bus cycle immediately before hi-z: high-impedance
preliminary user?s manual a13971ej7v0um 48 chapter 3 cpu the cpu of the NB85E, which is based on a risc architecture, executes almost all instructions in one clock cycle due to its five-stage pipeline control. 3.1 features ? advanced 32-bit architecture for embedded control ? number of instructions: 81 ? number of 32-bit general-purpose registers: 32 ? load/store instructions having long/short format ? three-operand instructions ? five-stage pipeline structure with one-clock pitch ? register/flag hazard interlock supported by hardware ? memory space program area: 64 mb linear address space data area: 4 gb linear address space ? instruction set suited to various application fields ? saturated calculation instructions ? bit manipulation instructions (set, clear, not, test) ? multiplication can be performed in 1 or 2 clocks due to on-chip hardware multiplier 16 bits 16 bits 32 bits 32 bits 32 bits 32 bits or 64 bits ? NB85E901 (rcu) interface function
chapter 3 cpu preliminary user?s manual a13971ej7v0um 49 3.2 registers the cpu registers can be classified into program registers, which are used by programs, and system registers, which are used to control the execution environment. all registers are 32-bit registers. figure 3-1. list of cpu registers (a) program registers r0 (zero register) r1 (assembler-reserved register) r2 r3 (stack pointer (sp)) r4 (global pointer (gp)) r5 (text pointer (tp)) r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 (element pointer (ep)) r31 (link pointer (lp)) pc (program counter) 0 31 (b) system registers eipc (register for saving status when interrupt occurs) eipsw (register for saving status when interrupt occurs) fepc (register for saving status when nmi occurs) fepsw (register for saving status when nmi occurs) ecr (interrupt source register) psw (program status word) ctpc (register for saving status when callt is executed) ctpsw (register for saving status when callt is executed) dbpc (register for saving status when exception is trapped) dbpsw (register for saving status when exception is trapped) ctbp (callt base pointer) 0 31
chapter 3 cpu preliminary user?s manual a13971ej7v0um 50 3.2.1 program registers the program registers include the general-purpose registers (r0 to r31) and the program counter (pc). table 3-1. list of program registers program register name function r0 zero register (always holds zero) r1 assembler-reserved register (used as a working register for address generation) r2 address/data variable register (when this register is not used by the real-time os) r3 stack pointer (used to generate a stack frame when a function is called) r4 global pointer (used to access a global variable of the data area) r5 text pointer (used as the register indicating the beginning of the text area (area for locating program code)) r6 to r29 registers for address/data variables r30 element pointer (used as the base pointer for address generation when accessing memory) general-purpose register r31 link pointer (used when the compiler calls a function) program counter pc holds instruction address during program execution remark for detailed explanations of r1, r3 to r5, and r31, which are used by the assembler or c compiler, refer to the c compiler package (ca850) user?s manual . (1) general-purpose registers the 32 registers r0 to r31 are provided as general-purpose registers. all of these registers can be used for data variables or address variables. however, take note of the following points when using the r0 to r5, r30, and r31 registers. (a) r0, r30 these registers are implicitly used by instructions. r0, which is a register that always holds 0, is used by operations that use 0, or in 0-offset addressing. r30 is used as a base pointer when accessing memory by the sld and sst instructions. (b) r1, r3 to r5, r31 these registers are implicitly used by the assembler and c compiler. the contents of these registers must be saved before they are used so that the contents are not destroyed, and the original contents must be returned after use. (c) r2 this register may be used by the real-time os. when not being used by the real-time os, r2 can be used as an address variable or data variable register.
chapter 3 cpu preliminary user?s manual a13971ej7v0um 51 (2) program counter this register holds the instruction address during program execution. the lower 26 bits are valid, and bits 31 to 26 are reserved for future function expansion (fixed at 0). if a carry from bit 25 to bit 26 occurs, it is ignored. also, bit 0 is fixed at 0, and no branching to an odd address can be performed. figure 3-2. program counter (pc) 31 26 25 10 pc000000 instruction address during program execution 0 after reset 00000000h
chapter 3 cpu preliminary user?s manual a13971ej7v0um 52 3.2.2 system registers system registers control the status of the cpu and hold interrupt information. to read from or write to these system registers, specify the system register number (see table 3-2 ) indicated by the system register load or store instruction (ldsr or stsr instruction). table 3-2. list of system registers name operation whether or not operand can be specified register no. ldsr instruction stsr instruction 0 eipc this register saves the value of the pc when a software exception or interrupt occurs. yes yes 1eipsw register for saving status when interrupt occurs note this register saves the value of the psw when a software exception or interrupt occurs. yes yes 2 fepc this register saves the value of the pc when a non- maskable interrupt (nmi) occurs. yes yes 3 fepsw register for saving status when nmi occurs this register saves the value of the psw when a non- maskable interrupt (nmi) occurs. yes yes 4 ecr interrupt source register this register holds information about the source when an exception or interrupt occurs. the exception code of a non-maskable interrupt (nmi) is set in the higher 16 bits of this register (fecc). the exception code of an exception or maskable interrupt is set in the lower 16 bits (eicc) (see figure 3-3 ). no yes 5 psw program status word this is a collection of flags indicating the program status (instruction execution result) or cpu status (see figure 3-4 ). yes yes 16 ctpc this register saves the value of the pc when a callt instruction is executed. yes yes 17 ctpsw register for saving status when callt is executed this register saves the value of the psw when a callt instruction is executed. yes yes 18 dbpc this register saves the value of the pc when an exception trap is generated due to the detection of an illegal instruction code. no yes 19 dbpsw register for saving status when exception is trapped this register saves the value of the psw when an exception trap is generated due to the detection of an illegal instruction code. no yes 20 ctbp callt base pointer this is used to specify the table address or generate the target address. yes yes 6 to 15, 21 to 31 reserved numbers for future function expansion (if these are accessed, operation is not guaranteed). no no note since there is only one set of these registers, their contents must be saved by the program when multiple interrupts are permitted. remark yes: access enabled no: access disabled
chapter 3 cpu preliminary user?s manual a13971ej7v0um 53 caution when interrupt servicing is performed and control is returned by the reti instruction after bit 0 of the eipc, fepc, or ctpc had been set (1) by the ldsr instruction, bit 0 is ignored (because bit 0 of the pc is fixed at 0). when setting a value in eipc, fepc, or ctpc, set an even value (bit 0 = 0) as long as there is no specific reason not to. figure 3-3. interrupt source register (ecr) 31 16 15 0 ecr fecc eicc after reset 00000000h bit position bit name function 31 to 16 fecc exception code of non-maskable interrupt (nmi) (see table 8-1 interrupt/exception list .) 15 to 0 eicc exception code of exception or maskable interrupt (see table 8-1 interrupt/exception list .)
chapter 3 cpu preliminary user?s manual a13971ej7v0um 54 figure 3-4. program status word (psw) 31 876543210 psw000000000000000000000000 np ep id sat cy ov sz after reset 00000020h bit position bit name function 7 np indicates that non-maskable interrupt servicing is in progress. when the non-maskable interrupt is acknowledged, this flag is set (1) to disable multiple interrupts. 0: non-maskable interrupt servicing is not in progress 1: non-maskable interrupt servicing is in progress 6 ep indicates that exception processing is in progress. this flag is set (1) when an exception is generated. interrupt requests are acknowledged even if this bit is set. 0: exception processing is not in progress 1: exception processing is in progress 5 id indicates whether or not maskable interrupt requests can be acknowledged. 0: interrupts are enabled 1: interrupts are disabled 4 sat indicates that the calculation result of a saturated calculation processing instruction overflowed and the calculation result is saturated. this flag, which is called the saturation flag, is set (1) when the calculation result of a saturated calculation instruction is saturated, and it is not cleared (0) even if the calculation results of subsequent instructions are not saturated. when this flag is cleared (0), data is loaded in the psw. this bit is neither set (1) nor cleared (0) by a general arithmetic calculation. 0: it is not saturated 1: it is saturated 3 cy indicates whether or not a carry or borrow occurred in the calculation result. 0: no carry or borrow occurred 1: a carry or borrow occurred 2 ov indicates whether or not an overflow occurred during the calculation. 0: no overflow occurred 1: an overflow occurred 1 s indicates whether or not the calculation result is negative. 0: the calculation result is positive or zero 1: the calculation result is negative 0 z indicates whether or not the calculation result is zero. 0: the calculation result is not zero 1: the calculation result is zero
chapter 3 cpu preliminary user?s manual a13971ej7v0um 55 3.3 address space the cpu of the NB85E supports a linear address space with a maximum size of 4 gb. memory and i/o are located in this address space (memory mapped i/o method). figure 3-5. address space data area (4 gb linear) 00000000h 03ffffffh 04000000h ffffffffh program area (64 mb linear) address space
chapter 3 cpu preliminary user?s manual a13971ej7v0um 56 3.3.1 program area for instruction addressing, the cpu of the NB85E supports a linear address space (program area) with a maximum size of 64 mb. figure 3-6. program area peripheral i/o area (4 kb) ram area (4, 12, 28, or 60 kb) 3ffffffh 3fff000h 3ffefffh rom area note (1 mb) 00fffffh 0100000h 0000000h 64 mb external memory area note when a low-level signal is input to the ifirome pin, this is also used as the external memory area. when a high-level signal is input to the ifirob2 pin, this is also used as the external memory area, and the rom area is located in the 1 mb area starting at address 0100000h.
chapter 3 cpu preliminary user?s manual a13971ej7v0um 57 3.3.2 data area for operand addressing (data access), the cpu of the NB85E supports a linear address space (data area) with a maximum size of 4 gb. the rom, ram, and peripheral i/o areas are each located in 64 mb or 256 mb address spaces. the size setting is selected according to the input level to the ifid256 pin. (1) 64 mb mode when a low-level signal is input to the ifid256 pin, the data area is set to 64 mb mode. in this mode, the 64 mb physical address space can be viewed as 64 images in the 4 gb address space. that is, the same 64 mb physical address space is accessed regardless of the values of bits 31 to 26 of the cpu address. figure 3-7. data area (64 mb mode) image data area (4 gb) image image 00000000h 03ffffffh 04000000h ffffffffh peripheral i/o area (4 kb) ram area (4, 12, 28, or 60 kb) 3ffffffh 3fff000h 3ffefffh rom area note (1 mb) 00fffffh 0100000h 0000000h program area (64 mb) external memory area ? image note when a low-level signal is input to the ifirome pin, this is also used as the external memory area. when a high-level signal is input to the ifirob2 pin, this is also used as the external memory area, and the rom area is located in the 1 mb area starting at address 0100000h.
chapter 3 cpu preliminary user?s manual a13971ej7v0um 58 (2) 256 mb mode when a high-level signal is input to the ifid256 pin, the data area is set to 256 mb mode. in this mode, the 256 mb physical address space can be viewed as 16 images in the 4 gb address space. that is, the same 256 mb physical address space is accessed regardless of the values of bits 31 to 28 of the cpu address. figure 3-8. data area (256 mb mode) peripheral i/o area (4 kb) ram area (4, 12, 28, or 60 kb) 256 mb external memory area same area note 2 ffff000h fffefffh image 4 gb image image image . . . 00000000h 0fffffffh 10000000h ffffffffh fffffffh 00fffffh 0100000h 0000000h 3ffffffh 4000000h 3fff000h 3ffefffh access prohibited area ram area (4, 12, 28, or 60 kb) external memory area rom area note 1 (1 mb) notes 1. when a low-level signal is input to the ifirome pin, this is also used as the external memory area. when a high-level signal is input to the ifirob2 pin, this is also used as the external memory area, and the rom area is located in the 1 mb area starting at address 0100000h. 2. when data is written to the ram area at address fffefffh and below in 256 mb mode, data having the same contents is also written to the area at address 3ffefffh and below, which is indicated by ?same area? in the figure. the contents of these areas are linked (a memory access is performed from the ram area at address 3ffefffh and below). caution addresses 3fff000h to 3ffffffh are an access prohibited area. the operation is not guaranteed when that area is accessed.
chapter 3 cpu preliminary user?s manual a13971ej7v0um 59 3.4 areas 3.4.1 rom area if a high level is input to the ifirome pin, the area of rom that can be accessed when rom is connected to vfb is set. (1) rom relocation function a 1 mb area at addresses 00000000h to 000fffffh or addresses 00100000h to 001fffffh is reserved as the rom area. the area where it is to be located is selected according to the input level to the ifirob2 pin. (2) interrupt/exception table the NB85E increases the interrupt response speed by assigning fixed jump destination addresses corresponding to interrupts or exceptions. this set of jump destination addresses is called the interrupt/exception table and is located at address 00000000h and following. when an interrupt/exception request is acknowledged, processing jumps to the jump destination address and the program that is written in memory beginning at that address is executed. remark when address 00000000h is set in the external memory area, prepare the jump destination address for jumping to the reset routine at address 00000000h of the external memory. figure 3-9. rom area (a) when ifirob2 = low level 00000000h 000fffffh 00100000h interrupt/exception table rom area external memory area (b) when ifirob2 = high level 00000000h 000fffffh 00100000h interrupt/exception table 001fffffh 00200000h external memory area rom area external memory area
chapter 3 cpu preliminary user?s manual a13971ej7v0um 60 table 3-3. interrupt/exception table starting address interrupt/exception source starting address interrupt/exception source starting address interrupt/exception source 00000000h reset 00000190h int17 00000310h int41 00000010h nmi0 000001a0h int18 00000320h int42 00000020h nmi1 000001b0h int19 00000330h int43 00000030h nmi2 000001c0h int20 00000340h int44 00000040h trap0n (n = 0 to fh) 000001d0h int21 00000350h int45 00000050h trap1n (n = 0 to fh) 000001e0h int22 00000360h int46 00000060h ilgop 000001f0h int23 00000370h int47 00000080h int0 00000200h int24 00000380h int48 00000090h int1 00000210h int25 00000390h int49 000000a0h int2 00000220h int26 000003a0h int50 000000b0h int3 00000230h int27 000003b0h int51 000000c0h int4 00000240h int28 000003c0h int52 000000d0h int5 00000250h int29 000003d0h int53 000000e0h int6 00000260h int30 000003e0h int54 000000f0h int7 00000270h int31 000003f0h int55 00000100h int8 00000280h int32 00000400h int56 00000110h int9 00000290h int33 00000410h int57 00000120h int10 000002a0h int34 00000420h int58 00000130h int11 000002b0h int35 00000430h int59 00000140h int12 000002c0h int36 00000440h int60 00000150h int13 000002d0h int37 00000450h int61 00000160h int14 000002e0h int38 00000460h int62 00000170h int15 000002f0h int39 00000470h int63 00000180h int16 00000300h int40 ? ? remark for the sources of interrupts or exceptions, see table 8-1 interrupt/exception list .
chapter 3 cpu preliminary user?s manual a13971ej7v0um 61 3.4.2 ram area in 64 mb mode, the area at address 3ffefffh and below is reserved as the area for ram connected to the vdb. in 256 mb mode, the address at fffefffh and below is reserved. the size of the ram area, which can be selected from among 4 kb, 12 kb, 28 kb, and 60 kb, is set according to the input levels to the ifra64, ifra32, and ifra16 pins. table 3-4. ram area size settings ifira64 ifira32 ifira16 ram area size lll4 kb l l h 12 kb l h arbitrary 28 kb h arbitrary arbitrary 60 kb remark l: low-level input h: high-level input figure 3-10. ram area (a) when 4 kb is selected ram area xffefffh xffe000h (b) when 12 kb is selected ram area xffefffh xffc000h (c) when 28 kb is selected ram area xffefffh xff8000h (d) when 60 kb is selected ram area xffefffh xff0000h set as follows if the size of the ram area to be used is other than 4 kb, 12 kb, 28 kb, or 60 kb.
chapter 3 cpu preliminary user?s manual a13971ej7v0um 62 (a) ram area size = 0 kb (ram-less) set the ram area size to 4 kb and handle the vdb pins as indicated in 2.3 recommended connection of unused pins . (b) 0 kb < ram area size < 4 kb set the ram area size to 4 kb and use from the lower side addresses as ram area. (c) 4 kb < ram area size < 12 kb set the ram area size to 12 kb and use from the lower side addresses as ram area. (d) 12 kb < ram area size < 28 kb set the ram area size to 28 kb and use from the lower side addresses as ram area. (e) 28 kb < ram area size < 60 kb set the ram area size to 60 kb and use from the lower side addresses as ram area. (f) 60 kb < ram area size a ram area size exceeding 60 kb cannot be set. example memory map when 8 kb ram is used. 3.4.3 peripheral i/o area in 64 mb mode, the area at address 3ffffffh and below is reserved as a peripheral i/o area. in 256 mb mode, the address at fffffffh and below is reserved. peripheral i/o registers to which functions have been assigned such as status monitoring or specification of the operating mode of the NB85E, memory controller (memc), or instruction/data cache are located in this area. for information about assigned registers, see 3.5 peripheral i/o registers . caution user-defined addresses must be assigned to the following areas only (user-usable area); all other addresses are reserved and cannot therefore be used. ? ? ? ? xfff200h to xfff47fh ? ? ? ? xfff520h to xfff7bfh ? ? ? ? xfff800h to xffffffh ram area xffefffh xffc000h xffe000h xffdfffh the ram area size is set to 12 kb the 8 kb from lower side addresses are ram area
chapter 3 cpu preliminary user?s manual a13971ej7v0um 63 figure 3-11. peripheral i/o area remark interrupts are not acknowledged between the store instruction and the subsequent instruction for the shaded area (refer to 8.7 periods when interrupts cannot be acknowledged ). peripheral i/o area xfff06fh xfff070h xfff1ffh xfff200h xfff47fh xfff480h reserved area (memc control register) user-usable area xfff4ffh xfff500h reserved area xfff51fh xfff520h xffffffh xfff07fh xfff080h xfff000h xfff05fh xfff060h xffefffh reserved area xfff7ffh xfff800h xfff7bfh xfff7c0h user-usable area xfff100h xfff0ffh reserved area reserved area (NB85E control register) reserved area (instruction/data cache control register) xfff900h xfff8ffh xfffa00h xfff9ffh user-usable area reserved area (NB85E control register)
chapter 3 cpu preliminary user?s manual a13971ej7v0um 64 3.4.4 external memory area access to the external memory area is made using the vdcsz7 to vdcsz0 signals assigned to each bank (see 4.2 memory banks ). the ?programmable peripheral i/o area?, which is independent of the peripheral i/o area, is also assigned to this area (see 4.4 programmable peripheral i/o area selection function ). caution rom, ram, and peripheral i/o areas cannot be accessed as external memory areas. 3.5 peripheral i/o registers (1) only the lower 12 bits of a 32-bit address are used for register address decoding, after being allocated to the 4 kb area of xxxxx 000h to xxxxx fffh. (2) the lowest bit of the address is not decoded. therefore, when the register of an odd address (2n + 1 address) is byte-accessed, the register of an even address (2n) will be accessed. (3) although word-accessible registers do not exist in the NB85E, halfword access using the lower and higher bits (in that order and ignoring the lowest 2) of a word area can be made twice to enable word access. (4) when byte-accessible registers are halfword-accessed, the higher 8 bits become undefined in a read operation, and the lower 8 bits of data are written to a register in a write operation. (5) registers other than those that control the NB85E are incorporated in each macro (memc, instruction/data cache).
chapter 3 cpu preliminary user?s manual a13971ej7v0um 65 3.5.1 NB85E control registers (1/4) address register name symbol r/w bit units for manipulation after reset 1 bit 8 bits 16 bits fffff 060h chip area select control register 0 csc0 r/w 2c11h fffff 062h chip area select control register 1 csc1 r/w 2c11h fffff 064h peripheral i/o area select control register bpc r/w 0000h fffff 066h bus size configuration register bsc r/w 0000h/ 5555h/ aaaah fffff 068h endian configuration register bec r/w 0000h fffff06ah cache configuration register bhc r/w 0000h fffff06eh npb strobe wait control register vswc r/w ? 77h fffff 080h dma source address register 0l dsa0l r/w undefined fffff 082h dma source address register 0h dsa0h r/w undefined fffff 084h dma destination address register 0l dda0l r/w undefined fffff 086h dma destination address register 0h dda0h r/w undefined fffff 088h dma source address register 1l dsa1l r/w undefined fffff08ah dma source address register 1h dsa1h r/w undefined fffff08ch dma destination address register 1l dda1l r/w undefined fffff08eh dma destination address register 1h dda1h r/w undefined fffff 090h dma source address register 2l dsa2l r/w undefined fffff 092h dma source address register 2h dsa2h r/w undefined fffff 094h dma destination address register 2l dda2l r/w undefined fffff 096h dma destination address register 2h dda2h r/w undefined fffff 098h dma source address register 3l dsa3l r/w undefined fffff09ah dma source address register 3h dsa3h r/w undefined fffff09ch dma destination address register 3l dda3l r/w undefined fffff09eh dma destination address register 3h dda3h r/w undefined fffff0c0h dma transfer count register 0 dbc0 r/w undefined fffff0c2h dma transfer count register 1 dbc1 r/w undefined fffff0c4h dma transfer count register 2 dbc2 r/w undefined fffff0c6h dma transfer count register 3 dbc3 r/w undefined fffff0d0h dma addressing control register 0 dadc0 r/w 0000h fffff0d2h dma addressing control register 1 dadc1 r/w 0000h fffff0d4h dma addressing control register 2 dadc2 r/w 0000h fffff0d6h dma addressing control register 3 dadc3 r/w 0000h fffff0e0h dma channel control register 0 dchc0 r/w ? 00h fffff0e2h dma channel control register 1 dchc1 r/w ? 00h fffff0e4h dma channel control register 2 dchc2 r/w ? 00h fffff0e6h dma channel control register 3 dchc3 r/w ? 00h fffff0f0h dma disable status register ddis r ? 00h
chapter 3 cpu preliminary user?s manual a13971ej7v0um 66 (2/4) address register name symbol r/w bit units for manipulation after reset 1 bit 8 bits 16 bits fffff0f2h dma restart register drst r/w ? 00h fffff 100h interrupt mask register 0 imr0 r/w ffffh fffff100h interrupt mask register 0l imr0l r/w ? ffh fffff101h interrupt mask register 0h imr0h r/w ? ffh fffff 102h interrupt mask register 1 imr1 r/w ffffh fffff102h interrupt mask register 1l imr1l r/w ? ffh fffff103h interrupt mask register 1h imr1h r/w ? ffh fffff 104h interrupt mask register 2 imr2 r/w ffffh fffff104h interrupt mask register 2l imr2l r/w ? ffh fffff105h interrupt mask register 2h imr2h r/w ? ffh fffff 106h interrupt mask register 3 imr3 r/w ffffh fffff106h interrupt mask register 3l imr3l r/w ? ffh fffff107h interrupt mask register 3h imr3h r/w ? ffh fffff 110h interrupt control register 0 pic0 r/w ? 47h fffff 112h interrupt control register 1 pic1 r/w ? 47h fffff 114h interrupt control register 2 pic2 r/w ? 47h fffff 116h interrupt control register 3 pic3 r/w ? 47h fffff 118h interrupt control register 4 pic4 r/w ? 47h fffff11ah interrupt control register 5 pic5 r/w ? 47h fffff11ch interrupt control register 6 pic6 r/w ? 47h fffff11eh interrupt control register 7 pic7 r/w ? 47h fffff 120h interrupt control register 8 pic8 r/w ? 47h fffff 122h interrupt control register 9 pic9 r/w ? 47h fffff 124h interrupt control register 10 pic10 r/w ? 47h fffff 126h interrupt control register 11 pic11 r/w ? 47h fffff 128h interrupt control register 12 pic12 r/w ? 47h fffff12ah interrupt control register 13 pic13 r/w ? 47h fffff12ch interrupt control register 14 pic14 r/w ? 47h fffff12eh interrupt control register 15 pic15 r/w ? 47h fffff 130h interrupt control register 16 pic16 r/w ? 47h fffff 132h interrupt control register 17 pic17 r/w ? 47h fffff 134h interrupt control register 18 pic18 r/w ? 47h fffff 136h interrupt control register 19 pic19 r/w ? 47h fffff 138h interrupt control register 20 pic20 r/w ? 47h fffff13ah interrupt control register 21 pic21 r/w ? 47h fffff13ch interrupt control register 22 pic22 r/w ? 47h fffff13eh interrupt control register 23 pic23 r/w ? 47h fffff 140h interrupt control register 24 pic24 r/w ? 47h
chapter 3 cpu preliminary user?s manual a13971ej7v0um 67 (3/4) address register name symbol r/w bit units for manipulation after reset 1 bit 8 bits 16 bits fffff 142h interrupt control register 25 pic25 r/w ? 47h fffff 144h interrupt control register 26 pic26 r/w ? 47h fffff 146h interrupt control register 27 pic27 r/w ? 47h fffff 148h interrupt control register 28 pic28 r/w ? 47h fffff14ah interrupt control register 29 pic29 r/w ? 47h fffff14ch interrupt control register 30 pic30 r/w ? 47h fffff14eh interrupt control register 31 pic31 r/w ? 47h fffff 150h interrupt control register 32 pic32 r/w ? 47h fffff 152h interrupt control register 33 pic33 r/w ? 47h fffff 154h interrupt control register 34 pic34 r/w ? 47h fffff 156h interrupt control register 35 pic35 r/w ? 47h fffff 158h interrupt control register 36 pic36 r/w ? 47h fffff15ah interrupt control register 37 pic37 r/w ? 47h fffff15ch interrupt control register 38 pic38 r/w ? 47h fffff15eh interrupt control register 39 pic39 r/w ? 47h fffff 160h interrupt control register 40 pic40 r/w ? 47h fffff 162h interrupt control register 41 pic41 r/w ? 47h fffff 164h interrupt control register 42 pic42 r/w ? 47h fffff 166h interrupt control register 43 pic43 r/w ? 47h fffff 168h interrupt control register 44 pic44 r/w ? 47h fffff16ah interrupt control register 45 pic45 r/w ? 47h fffff16ch interrupt control register 46 pic46 r/w ? 47h fffff16eh interrupt control register 47 pic47 r/w ? 47h fffff 170h interrupt control register 48 pic48 r/w ? 47h fffff 172h interrupt control register 49 pic49 r/w ? 47h fffff 174h interrupt control register 50 pic50 r/w ? 47h fffff 176h interrupt control register 51 pic51 r/w ? 47h fffff 178h interrupt control register 52 pic52 r/w ? 47h fffff17ah interrupt control register 53 pic53 r/w ? 47h fffff17ch interrupt control register 54 pic54 r/w ? 47h fffff17eh interrupt control register 55 pic55 r/w ? 47h fffff 180h interrupt control register 56 pic56 r/w ? 47h fffff 182h interrupt control register 57 pic57 r/w ? 47h fffff 184h interrupt control register 58 pic58 r/w ? 47h fffff 186h interrupt control register 59 pic59 r/w ? 47h fffff 188h interrupt control register 60 pic60 r/w ? 47h fffff18ah interrupt control register 61 pic61 r/w ? 47h fffff18ch interrupt control register 62 pic62 r/w ? 47h
chapter 3 cpu preliminary user?s manual a13971ej7v0um 68 (4/4) address register name symbol r/w bit units for manipulation after reset 1 bit 8 bits 16 bits fffff18eh interrupt control register 63 pic63 r/w ? 47h fffff1fah in-service priority register ispr r ? 00h fffff1fch command register prcmd w undefined fffff1feh power save control register psc r/w ? 00h 3.5.2 memory controller (memc) control registers address register name symbol r/w bit units for manipulation after reset 1 bit 8 bits 16 bits fffff 480h bus cycle type configuration register 0 bct0 r/w note 1 fffff 482h bus cycle type configuration register 1 bct1 r/w note 1 fffff 484h data wait control register 0 dwc0 r/w 7777h fffff 486h data wait control register 1 dwc1 r/w 7777h fffff 488h bus cycle control register bcc r/w ffffh fffff48ah address setting wait control register asc r/w ffffh fffff48ch bus cycle period control register bcp r/w ? note 2 fffff49ah page rom configuration register prc r/w 7000h fffff4a0h sdram configuration register 0 scr0 r/w 0000h fffff4a2h sdram refresh control register 0 rfs0 r/w 0000h fffff4a4h sdram configuration register 1 scr1 r/w 0000h fffff4a6h sdram refresh control register 1 rfs1 r/w 0000h fffff4a8h sdram configuration register 2 scr2 r/w 0000h fffff4aah sdram refresh control register 2 rfs2 r/w 0000h fffff4ach sdram configuration register 3 scr3 r/w 0000h fffff4aeh sdram refresh control register 3 rfs3 r/w 0000h fffff4b0h sdram configuration register 4 scr4 r/w 0000h fffff4b2h sdram refresh control register 4 rfs4 r/w 0000h fffff4b4h sdram configuration register 5 scr5 r/w 0000h fffff4b6h sdram refresh control register 5 rfs5 r/w 0000h fffff4b8h sdram configuration register 6 scr6 r/w 0000h fffff4bah sdram refresh control register 6 rfs6 r/w 0000h fffff4bch sdram configuration register 7 scr7 r/w 0000h fffff4beh sdram refresh control register 7 rfs7 r/w 0000h notes 1. the value differs as follows, depending on the level input to the mce pin of the memc (NB85E500/ nu85e500). high level input to mce: 8888h low level input to mce: 0000h 2. the value differs as follows, depending on the level input to the bcpen pin of the memc (NB85E500/ nu85e500). high level input to bcpen: 80h low level input to bcpen: 00h
chapter 3 cpu preliminary user?s manual a13971ej7v0um 69 3.5.3 instruction cache control registers address register name symbol r/w bit units for manipulation after reset 1 bit 8 bits 16 bits fffff 070h instruction cache control register icc r/w 0003h note 1 fffff070h instruction cache control register l iccl r/w ? 03h note 2 fffff071h instruction cache control register h icch r/w ? 00h fffff 074h instruction cache data configuration register icd r/w undefined notes 1. this value becomes 0003h when the reset signal is active, and tag initialization starts automatically. the value changes to 0000h upon the completion of tag initialization. 2. this value becomes 03h when the reset signal is active, and tag initialization starts automatically. the value changes to 00h upon the completion of tag initialization. 3.5.4 data cache control registers address register name symbol r/w bit units for manipulation after reset 1 bit 8 bits 16 bits fffff 078h data cache control register dcc r/w 0003h note fffff07ch data cache data configuration register dcd r/w undefined note this value becomes 0003h when the reset signal is active, and tag initialization starts automatically. the value changes to 0000h upon the completion of tag initialization.
chapter 3 cpu preliminary user?s manual a13971ej7v0um 70 3.6 NB85E901 (rcu) interface 3.6.1 outline the rcu interface is a bus interface for connecting the NB85E to the run control unit (rcu). the rcu communicates with an n-wire type in-circuit emulator by using jtag and executes debug processing. figure 3-12. connection of NB85E and n-wire type in-circuit emulator via rcu NB85E jtag rcu n-wire type in-circuit emulator 3.6.2 on-chip debugging by connecting the rcu to the NB85E, on-chip debugging (an on-board debug function) can be realized. the cpu of the NB85E is equipped with a breakpoint function, which can detect breakpoints based on the execution address, access address, access data, range (address mask), or 2-stage sequential execution, as well as a break interrupt function operable by external port input. connection of the rcu to the NB85E allows not only debugging using these functions, but also makes possible the employment of a background monitor jtag system rom emulator and an n- wire type in-circuit emulator. for details, refer to chapter 10 NB85E901. remark the NB85Et has an on-chip debug control unit (dcu) that is equipped with an rcu, trcu (trace control unit), and teu (trigger event unit). this dcu enables all of the break functions of the cpu to be used in addition to pc trace (branch trace) and data access trace functions and event detection functions that can detect events according to the execution address, access address, access data, range (size comparison), or four-stage sequential execution.
preliminary user?s manual a13971ej7v0um 71 chapter 4 bcu the bus control unit (bcu), which operates as a bus master on the vsb, controls the on-chip bus bridge (bbr), test interface control unit (tic), and peripheral macros (bus slaves) such as the external memory controller (memc) connected to the vsb. 4.1 features ? 32-bit independent bi-directional data bus ? one bus clock transfer between consecutive clock falling edges ? data transfer in 8-bit, 16-bit, or 32-bit units on a 32-bit bus by means of the bus size function ? bus arbitration for a multi-master system ? programmable chip select function ? programmable peripheral i/o area select function ? endian setting function 4.2 memory banks the data area is subdivided into multiple units called banks. the bcu makes bus size, endian, and cache settings in terms of units called ?csn area?, which are arbitrary combinations of banks. ?csn area? settings are made based on the vdcszn signals corresponding to each bank (n = 7 to 0).
chapter 4 bcu preliminary user?s manual a13971ej7v0um 72 (1) memory banks for 64 mb mode the 64 mb data area is subdivided into memory banks with sizes of 2 mb, 4 mb, and 8 mb. bank 0 (2 mb) 01fffffh 0200000h 0000000h bank 1 (2 mb) 03fffffh 0400000h bank 2 (2 mb) 05fffffh 0600000h bank 3 (2 mb) 07fffffh 0800000h bank 4 (4 mb) 0bfffffh 0c00000h bank 5 (4 mb) 0ffffffh 1000000h bank 6 (8 mb) 17fffffh 1800000h bank 7 (8 mb) 1ffffffh 2000000h bank 8 (8 mb) 27fffffh 2800000h bank 9 (8 mb) 2ffffffh 3000000h bank 10 (4 mb) 33fffffh 3400000h bank 11 (4 mb) 37fffffh 3800000h bank 12 (2 mb) 39fffffh 3a00000h bank 13 (2 mb) 3bfffffh 3c00000h bank 14 (2 mb) 3dfffffh 3e00000h bank 15 (2 mb) 3ffffffh peripheral i/o area (4 kb) ram area (4 k, 12 k, 28 k, or 60 kb) external memory area 3fff000h 3ffffffh 3ffefffh 3e00000h external memory area (1 mb) rom area note (1 mb) [when a high-level signal is input to the ifirome pin ] 0100000h 01fffffh 00fffffh 0000000h external memory area 64mb note when a low-level signal is input to the ifirome pin, this is also used as the external memory area.
chapter 4 bcu preliminary user?s manual a13971ej7v0um 73 (2) memory banks for 256 mb mode the 256 mb data area is subdivided into four areas (area 0 to area 3), each of which contain memory banks of size 2 mb. bank 12 (2 mb) peripheral i/o area (4 kb) ram area (4 k, 12 k, 28 k, or 60 kb) area 3 01fffffh 0200000h 0000000h 03fffffh 0400000h 05fffffh 0600000h 07fffffh 0800000h 3ffffffh 4000000h 7ffffffh 8000000h bffffffh c000000h f7fffffh f800000h f9fffffh fa00000h fbfffffh fc00000h fdfffffh fe00000h fffffffh ffff000h fffffffh fffefffh fe00000h 0100000h 01fffffh 00fffffh 0000000h external memory area external memory area (1 mb) rom area note 2 (1 mb) [when a high-level signal is input to the ifirome pin] 256 mb external memory area 3ffefffh 3fff000h bank 13 (2 mb) bank 14 (2 mb) bank 15 (2 mb) area 2 area 1 area 0 bank 0 (2 mb) bank 1 (2 mb) bank 2 (2 mb) bank 3 (2 mb) same area note 1 notes 1. see figure 3-8 data area (256 mb mode) . notes 2. when a low-level signal is input to the ifirome pin, this is also used as the external memory area.
chapter 4 bcu preliminary user?s manual a13971ej7v0um 74 4.3 programmable chip select function the vdcszn signals corresponding to each bank of memory are set and the data area is subdivided into multiple csn areas according to the chip area select control registers (csc0 and csc1) (n = 7 to 0). the csc0 and csc1 registers can be read or written in 16-bit units. when the vdcszn signals for the same bank overlap due to the csc0 and csc1 register settings, the signal prioritization is as follows. ? vdcsz0 > vdcsz2 > vdcsz1 > vdcsz3 ? vdcsz7 > vdcsz5 > vdcsz6 > vdcsz4 figure 4-1. chip area select control register 0 (csc0) 1514131211109876543210 csc0 cs 33 cs 32 cs 31 cs 30 cs 23 cs 22 cs 21 cs 20 cs 13 cs 12 cs 11 cs 10 cs 03 cs 02 cs 01 cs 00 address fffff060h after reset 2c11h bit position bit name function 15 to 0 csn3 to csn0 when each bit is set (1), the vdcszn signal becomes active if the condition within parentheses holds. bit name vdcszn signal that becomes active 64 mb mode 256 mb mode cs00 vdcsz0 (when accessing bank 0) cs01 vdcsz0 (when accessing bank 1) cs02 vdcsz0 (when accessing bank 2) cs03 vdcsz0 (when accessing bank 3) cs10 vdcsz1 (when accessing bank 0 or 1) cs11 vdcsz1 (when accessing bank 2 or 3) vdcsz1 (when accessing area 0) (same when each bit is cleared (0)) cs12 vdcsz1 (when accessing bank 4) cs13 vdcsz1 (when accessing bank 5) cs20 vdcsz2 (when accessing bank 0) cs21 vdcsz2 (when accessing bank 1) cs22 vdcsz2 (when accessing bank 2) cs23 vdcsz2 (when accessing bank 3) cs30 vdcsz3 (when accessing bank 0, 1, 2, or 3) cs31 vdcsz3 (when accessing bank 4 or 5) vdcsz3 (when accessing area 1) (same when each bit is cleared (0)) cs32 vdcsz3 (when accessing bank 6) cs33 vdcsz3 (when accessing bank 7) remark n = 3 to 0
chapter 4 bcu preliminary user?s manual a13971ej7v0um 75 figure 4-2. chip area select control register 1 (csc1) 1514131211109876543210 csc1 cs 43 cs 42 cs 41 cs 40 cs 53 cs 52 cs 51 cs 50 cs 63 cs 62 cs 61 cs 60 cs 73 cs 72 cs 71 cs 70 address fffff062h after reset 2c11h bit position bit name function 15 to 0 csn3 to csn0 when each bit is set (1), the vdcszn signal becomes active if the condition within parentheses holds. bit name vdcszn signal that becomes active 64 mb mode 256 mb mode cs40 vdcsz4 (when accessing bank 12, 13, 14, or 15) vdcsz4 (when accessing area 2) (same when each bit is cleared (0)) cs41 vdcsz4 (when accessing bank 10 or 11) cs42 vdcsz4 (when accessing bank 9) cs43 vdcsz4 (when accessing bank 8) cs50 vdcsz5 (when accessing bank 15) cs51 vdcsz5 (when accessing bank 14) cs52 vdcsz5 (when accessing bank 13) cs53 vdcsz5 (when accessing bank 12) cs60 vdcsz6 (when accessing bank 14 or 15) cs61 vdcsz6 (when accessing bank 12 or 13) vdcsz6 (when accessing area 3) (same when each bit is cleared (0)) cs62 vdcsz6 (when accessing bank 11) cs63 vdcsz6 (when accessing bank 10) cs70 vdcsz7 (when accessing bank 15) cs71 vdcsz7 (when accessing bank 14) cs72 vdcsz7 (when accessing bank 13) cs73 vdcsz7 (when accessing bank 12) remark n = 4 to 7
chapter 4 bcu preliminary user?s manual a13971ej7v0um 76 examples 1. the following figure shows an example of csc0 and csc1 register settings for 64 mb mode and the memory map after the settings are made. figure 4-3. csc0 and csc1 register setting example (64 mb mode) (1/3) (a) csc0 register settings 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1514131211109876543210 csc0 vdcsz0 (when accessing bank 0) vdcszn signals that become active vdcsz0 (when accessing bank 1) vdcsz1 (when accessing bank 0 or 1) notes 1, 2 vdcsz1 (when accessing bank 2 or 3) notes 3, 4 vdcsz1 (when accessing bank 4) vdcsz1 (when accessing bank 5) vdcsz2 (when accessing bank 0) note 1 vdcsz2 (when accessing bank 1) note 2 vdcsz2 (when accessing bank 2) vdcsz2 (when accessing bank 3) vdcsz3 (when accessing bank 0, 1, 2, or 3) notes 1, 2, 3, 4 vdcsz3 (when accessing bank 4 or 5) notes 5, 6 vdcsz3 (when accessing bank 6) vdcsz3 (when accessing bank 7) notes 1. since the high priority signal from the bit 0 setting (vdcsz0) corresponds to bank 0, the setting in bank 0 becomes ineffective. notes 2. since the high priority signal from the bit 1 setting (vdcsz0) corresponds to bank 1, the setting in bank 1 becomes ineffective. notes 3. since the high priority signal from the bit 10 setting (vdcsz2) corresponds to bank 2, the setting in bank 2 becomes ineffective. notes 4. since the high priority signal from the bit 11 setting (vdcsz2) corresponds to bank 3, the setting in bank 3 becomes ineffective. notes 5. since the high priority signal from the bit 6 setting (vdcsz1) corresponds to bank 4, the setting in bank 4 becomes ineffective. notes 6. since the high priority signal from the bit 7 setting (vdcsz1) corresponds to bank 5, the setting in bank 5 becomes ineffective.
chapter 4 bcu preliminary user?s manual a13971ej7v0um 77 figure 4-3. csc0 and csc1 register setting example (64 mb mode) (2/3) (b) csc1 register settings 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 0 1514131211109876543210 csc1 vdcsz7 (when accessing bank 14) vdcszn signals that become active vdcsz7 (when accessing bank 13) vdcsz6 (when accessing bank 12 or 13) note 1 vdcsz6 (when accessing bank 11) vdcsz6 (when accessing bank 10) vdcsz5 (when accessing bank 15) vdcsz5 (when accessing bank 14) note 2 vdcsz5 (when accessing bank 13) note 3 vdcsz4 (when accessing bank 12, 13, 14, or 15) notes 2, 3, 4, 5 vdcsz4 (when accessing bank 10 or 11) notes 6, 7 vdcsz4 (when accessing bank 9) vdcsz4 (when accessing bank 8) notes 1. since the high priority signal from the bit 2 setting (vdcsz7) corresponds to bank 13, only the setting in bank 12 becomes effective. notes 2. since the high priority signal from the bit 1 setting (vdcsz7) corresponds to bank 14, the setting in bank 14 becomes ineffective. notes 3. since the high priority signal from the bit 2 setting (vdcsz7) corresponds to bank 13, the setting in bank 13 becomes ineffective. notes 4. since the high priority signal from the bit 5 setting (vdcsz6) corresponds to bank 12, the setting in bank 12 becomes ineffective. notes 5. since the high priority signal from the bit 8 setting (vdcsz5) corresponds to bank 15, the setting in bank 15 becomes ineffective. notes 6. since the high priority signal from the bit 7 setting (vdcsz6) corresponds to bank 10, the setting in bank 10 becomes ineffective. notes 7. since the high priority signal from the bit 6 setting (vdcsz6) corresponds to bank 11, the setting in bank 11 becomes ineffective.
chapter 4 bcu preliminary user?s manual a13971ej7v0um 78 figure 4-3. csc0 and csc1 register setting example (64 mb mode) (3/3) (c) memory map bank 0 (2m) [vdcsz0] bank 1 (2m) [vdcsz0] bank 2 (2m) [vdcsz2] bank 3 (2m) [vdcsz2] bank 4 (4m) [vdcsz1] bank 5 (4m) [vdcsz1] bank 6 (8m) [vdcsz3] bank 7 (8m) [vdcsz3] bank 8 (8m) [vdcsz4] bank 9 (8m) [vdcsz4] bank 10 (4m) [vdcsz6] bank 11 (4m) [vdcsz6] bank 12 (2m) [vdcsz6] bank 13 (2m) [vdcsz7] bank 14 (2m) [vdcsz7] bank 15 (2m) [vdcsz5] cs7 area cs6 area cs4 area cs3 area cs1 area cs2 area cs0 area cs5 area remark the values within parentheses indicate the size of each bank (unit: bytes). the values within brackets indicate the corresponding vdcszn signal (n = 7 to 0).
chapter 4 bcu preliminary user?s manual a13971ej7v0um 79 examples 2. the following figure shows an example of csc0 and csc1 register settings for 256 mb mode and the memory map after the settings are made. figure 4-4. csc0 and csc1 register setting example (256 mb mode) (1/2) (a) csc0 register settings x x x x 1 1 1 1 x x x x 0 1 0 1 1514131211109876543210 csc0 vdcsz0 (when accessing bank 0) vdcszn signals that become active vdcsz0 (when accessing bank 1) vdcsz1 (when accessing area 0) note 1 vdcsz2 (when accessing bank 0) note 2 vdcsz2 (when accessing bank 1) note 3 vdcsz2 (when accessing bank 2) vdcsz2 (when accessing bank 3) vdcsz3 (when accessing area 1) notes 1. since the high priority signals from the bit 0, 1, 10, and 11 settings (vdcsz0 and vdcsz2) correspond to banks 0 to 3, the setting in banks 0 to 3, which are included in area 0, become ineffective. notes 2. since the high priority signal from the bit 0 setting (vdcsz0) corresponds to bank 0, the setting becomes ineffective. notes 3. since the high priority signal from the bit 1 setting (vdcsz0) corresponds to bank 1, the setting becomes ineffective. (b) csc1 register settings x x x x 0 1 1 1 x x x x 0 1 1 0 1514131211109876543210 csc1 vdcsz7 (when accessing bank 14) vdcszn signals that become active vdcsz7 (when accessing bank 13) vdcsz6 (when accessing area 3) note 1 vdcsz5 (when accessing bank 15) vdcsz5 (when accessing bank 14) note 2 vdcsz5 (when accessing bank 13) note 3 vdcsz4 (when accessing area 2) notes 1. since the high priority signals from the bit 1, 2, and 8 settings (vdcsz5 and vdcsz7) correspond to banks 13 to 15, the settings in banks 13 to 15, which are included in area 3, become ineffective (since bank 12 has no corresponding vdcszn signal, its setting does not become ineffective). notes 2. since the high priority signal from the bit 1 setting (vdcsz7) corresponds to bank 14, the setting becomes ineffective. notes 3. since the high priority signal from the bit 2 setting (vdcsz7) corresponds to bank 13, the setting becomes ineffective.
chapter 4 bcu preliminary user?s manual a13971ej7v0um 80 figure 4-4. csc0 and csc1 register setting example (256 mb mode) (2/2) (c) memory map bank 0 (2m) [vdcsz0] bank 1 (2m) [vdcsz0] bank 2 (2m) [vdcsz2] bank 3 (2m) [vdcsz2] (bank 12 (2m)) bank 13 (2m) [vdcsz7] bank 14 (2m) [vdcsz7] bank 15 (2m) [vdcsz5] [vdcsz6] [vdcsz4] [vdcsz1] [vdcsz3] cs7 area cs6 area cs4 area cs3 area cs1 area cs2 area cs0 area cs5 area area 2 area 3 area 1 area 0 remark the values within parentheses indicate the size of each bank (unit: bytes). the values within brackets indicate the corresponding vdcszn signal (n = 7 to 0). 4.4 programmable peripheral i/o area selection function the NB85E has a 4 kb peripheral i/o area that is allocated in advance in the address space and a 12 kb programmable peripheral i/o area that can be allocated at arbitrary addresses according to register settings. registers for peripheral macros connected to the npb or user logic can be freely located in the programmable peripheral i/o area. caution be sure to allocate the programmable peripheral i/o area to a csn area in which both little endian and instruction/data cache-prohibited settings have been made (n = 7 to 0).
chapter 4 bcu preliminary user?s manual a13971ej7v0um 81 figure 4-5. peripheral i/o area and programmable peripheral i/o area (a) 64 mb mode (b) 256 mb mode (n = yy11b) peripheral i/o area (4 kb) (4 kb) programmable peripheral i/o area (12 kb) fffffffh ffff000h fffefffh 0000000h xxxnfffh xxxm000h 3fff000h 3ffefffh 3ffffffh 3fff000h 3ffefffh xxxnfffh xxxm000h 0000000h same area (m = yy00b) same area same area note peripheral i/o area (4 kb) (4 kb) programmable peripheral i/o area (12 kb) (ram area) (n = yy11b) (m = yy00b) note see figure 3-8 data area (256 mb mode) . remarks 1. xxx: setting according to the pa13 to pa02 bits of the bpc register yy: setting according to the pa01 and pa00 bits of the bpc register 2. since the areas indicated by ?same area? are linked, if data is written in one area, data having the same contents is also written in the other area.
chapter 4 bcu preliminary user?s manual a13971ej7v0um 82 the programmable peripheral i/o area can be used by specifying the higher 14 bits (bit 27 to bit 14) of the starting address in the pa00 to pa13 bits of the peripheral i/o area select control register (bpc) and setting (1) the pa15 bit. the bpc register can be read or written in 16-bit units. the prioritization of the various csn areas selected by the vdcszn signals and the programmable peripheral i/o area is as follows (n = 7 to 0). programmable peripheral i/o area > various csn areas selected by vdcszn signals cautions 1. in 64 mb mode, if the programmable peripheral i/o area overlaps the following areas, the programmable peripheral i/o area becomes invalid. ? ? ? ? peripheral i/o area ? ? ? ? rom area ? ? ? ? ram area 2. in 256 mb mode, if the programmable peripheral i/o area overlaps the following areas, the programmable peripheral i/o area becomes invalid. ? ? ? ? peripheral i/o area ? ? ? ? rom area ? ? ? ? ram area ? ? ? ? the area that is the same as the ram area and that is located at address 3ffefffh and below (see figure 3-8 data area (256 mb mode)) 3. if there are no peripheral macros connected to the npb or user logic, no programmable peripheral i/o area need be set (set the bpc register to its after-reset value). 4. when accessing the programmable peripheral i/o area, the vdcszn signals are all output as inactive (high level) (n = 7 to 0). 5. programmable peripheral i/o area address setting is enabled only once. do not change address in the middle of a program. figure 4-6. peripheral i/o area select control register (bpc) 1514131211109876543210 bpc pa 15 0 pa 13 pa 12 pa 11 pa 10 pa 09 pa 08 pa 07 pa 06 pa 05 pa 04 pa 03 pa 02 pa 01 pa 00 address fffff064h after reset 0000h bit position bit name function 15 pa15 sets whether or not the programmable peripheral i/o area can be accessed. 0: it cannot be accessed 1: it can be accessed 13 to 0 pa13 to pa00 specifies bit 27 to bit 14 of the starting address of the programmable peripheral i/o area. (the other bits are fixed at zero.) caution always set bit 14 to 0. if it is set to 1, operation is not guaranteed.
chapter 4 bcu preliminary user?s manual a13971ej7v0um 83 4.5 bus size setting function the bus size setting function uses the bus size configuration register (bsc) to set the vsb data bus size for each csn area selected by the chip select signals (vdcszn) (see figures 4-3 and 4-4 ) (n = 7 to 0). the bsc register can be read or written in 16-bit units. figure 4-7. bus size configuration register (bsc) 1514131211109876543210 bsc bs 71 bs 70 bs 61 bs 60 bs 51 bs 50 bs 41 bs 40 bs 31 bs 30 bs 21 bs 20 bs 11 bs 10 bs 01 bs 00 address fffff066h after reset note bit position bit name function 15 to 0 bsn1, bsn0 specifies the peripheral macro on the vsb that was located in the csn area and the data bus size. bsn1 bsn0 vsb data bus size 0 0 8 bits 0 1 16 bits 1 0 32 bits 1 1 setting prohibited remark n = 7 to 0 note the after-reset value differs as follows according to the input levels to the ifinsz1 and ifinsz0 pins. ifinsz1 ifinsz0 vsb data bus size after-reset value low level low level 32 bits aaaah low level high level 16 bits 5555h high level low level 8 bits 0000h example in a csn area, when the boot rom is 16-bit width and memories in other areas are 32-bit width, start up using 16-bit width in the initial state (input a low level to the ifinsz1 pin and a high level to the ifinsz0 pin) and then switch to 32-bit width via the bsc register.
chapter 4 bcu preliminary user?s manual a13971ej7v0um 84 4.6 endian setting function the endian setting function uses the endian configuration register (bec) to set the endian format of word data within memory for each csn area selected by the chip select signals (vdcszn) (see figures 4-3 and 4-4 ) (n = 7 to 0). the bec register can be read or written in 16-bit units. cautions 1. set the csn area specified as the programmable peripheral i/o area in the little endian format (n = 7 to 0). 2. each of the following areas is fixed at little endian format. any setting of the big endian format for these areas according to the bec register is invalid. ? ? ? ? peripheral i/o area ? ? ? ? rom area ? ? ? ? ram area ? ? ? ? the area that is the same as the ram area and that is located at address 3ffefffh and below (for 256 mb mode) (see figure 3-8 data area (256 mb mode)) ? ? ? ? external memory fetch area (when vbbstr signal is active) figure 4-8. endian configuration register (bec) 1514131211109876543210 bec 0 be 70 0 be 60 0 be 50 0 be 40 0 be 30 0 be 20 0 be 10 0 be 00 address fffff068h after reset 0000h bit position bit name function 14, 12, 10, 8, 6, 4, 2, 0 ben0 sets the endian format of word data in the csn area. ben0 endian format 0 little endian format (see figure 4-9 ) 1 big endian format (see figure 4-10 ) remark n = 7 to 0 caution always set bits 15, 13, 11, 9, 7, 5, 3, and 1 to 0. if they are set to 1, operation is not guaranteed.
chapter 4 bcu preliminary user?s manual a13971ej7v0um 85 figure 4-9. word data little endian format example 23 16 15 8 (0009h) 31 24 (000bh) 7 0 (0008h) (0006h) (0005h) (0007h) (0004h) (0002h) (0001h) (0003h) (0000h) (000ah) figure 4-10. word data big endian format example 23 16 15 8 (000ah) 31 24 (0008h) 7 0 (000bh) (0005h) (0006h) (0004h) (0007h) (0001h) (0002h) (0000h) (0003h) (0009h) 4.6.1 usage restrictions concerning big endian format with nec development tools (1) when using the debugger (id850) only the memory window display supports the big endian format. (2) when using the compiler (ca850) (a) c language restrictions (i) the following restrictions are attached to variables configured in a big endian space. <1> unions cannot be used. <2> bitfields cannot be used. <3> accesses based on the cast (changed access size) cannot be used. <4> variables with initial values cannot be used. (ii) because the access size may change due to optimization, it is necessary to specify the following optimization suppression options. ? for global optimization sections (opt850) ..................-wo, -xtb ? for model-based optimization sections (impr850).....-wi, +arg_reg_opt=off, +stld_trans_opt=off
chapter 4 bcu preliminary user?s manual a13971ej7v0um 86 however, it is unnecessary to specify the above optimization suppression options when not using ?cast? or ?mask/shift? access note . note the condition is that patterns causing the following optimization are not used. it is extremely difficult to perform a perfect check on the user side in a state such as where all the patterns (especially in the model-based optimization section) are mixed together. the above optimization suppression options are therefore recommended. <1> for global optimization section ? 1 bit set using bit or int i; i ^= 1; ? 1 bit clear using bit and i &= ~1; ? 1 bit not using bit xor i ^= 1; ? 1 bit test using bit and if(i & 1); <2> for model-based optimization section usage whereby identical variables are accessed in different sizes ? cast ? mask ? shift example int i, *ip; char c; : : c=*((char*)ip); : : c = 0xff & i; : : i = (i << 24) >> 24; (b) assembly language restrictions area-securing dummy instructions that are not byte size (.hword, .word, .float, .shword) cannot be used for variables configured in the big endian space.
chapter 4 bcu preliminary user?s manual a13971ej7v0um 87 4.7 cache configuration the cache configuration register (bhc) is used to set the cache memory configuration for each csn area selected by the chip select signals (vdcszn) (see figures 4-3 and 4-4 ) (n = 7 to 0). the bhc register can be read or written in 16-bit units. cautions 1. be sure to disable the cache for big endian format csn area and csn areas set as the following areas (n = 7 to 0). ? ? ? ? rom area ? ? ? ? ram area ? ? ? ? peripheral i/o area ? ? ? ? programmable peripheral i/o area 2. the instruction/data cache enabled setting (bhn0/bhn1 bit = 1 (set)) is only valid when a low level is being input (cache enabled) to the ifiunch0 or ifiunch1 pin (n = 7 to 0). 3. when using the data cache, set this register after setting the data cache?s data cache control register (dcc). figure 4-11. cache configuration register (bhc) 1514131211109876543210 bhc bh 71 bh 70 bh 61 bh 60 bh 51 bh 50 bh 41 bh 40 bh 31 bh 30 bh 21 bh 20 bh 11 bh 10 bh 01 bh 00 address fffff06ah after reset 0000h bit position bit name function 15, 13, 11, 9, 7, 5, 3, 1 bhn1 sets whether or not the data cache located in the csn area can be used. bhn1 data cache setting 0 cache disabled 1 cache enabled 14, 12, 10, 8, 6, 4, 2, 0 bhn0 sets whether or not the instruction cache located in the csn area can be used. bhn0 instruction cache setting 0 cache disabled 1 cache enabled remark n = 7 to 0
chapter 4 bcu preliminary user?s manual a13971ej7v0um 88 4.8 bcu-related register setting examples figure 4-12 shows a bpc, bsc, bec, and bhc register setting example, the corresponding settings for each csn area, and the memory map when the data area has been set according to the contents of the example shown in figure 4-3 csc0 and csc1 register setting example (64 mb mode) (n = 7 to 0) . figure 4-12. bpc, bsc, bec, bhc register setting example (1/3) (a) bpc register setting 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1514131211109876543210 bpc programmable peripheral i/o area: can be accessed programmable peripheral i/o area starting address: 2400000h (b) bsc register setting 1 1 0 0 0 1 0 1 0 0 0 0 1 1 0 0 1514131211109876543210 bsc cs0 area: 32 bits cs1 area: 32 bits cs2 area: 8 bits cs3 area: 8 bits cs4 area: 16 bits cs5 area: 16 bits cs6 area: 32 bits cs7 area: 32 bits vsb data bus size of csn area (c) bec register setting 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1514131211109876543210 bec cs0 area: little endian cs1 area: little endian cs2 area: little endian cs3 area: big endian cs4 area: little endian cs5 area: little endian cs6 area: little endian cs7 area: big endian endian format of csn area
chapter 4 bcu preliminary user?s manual a13971ej7v0um 89 figure 4-12. bpc, bsc, bec, bhc register setting example (2/3) (d) bhc register setting 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1514131211109876543210 bhc cs0 area: cache not available cs1 area: cache available cs2 area: cache not available cs3 area: cache not available cs4 area: cache not available cs5 area: cache not available cs6 area: cache not available cs7 area: cache not available instruction cache setting of csn area cs0 area: cache not available cs1 area: cache not available cs2 area: cache available cs3 area: cache not available cs4 area: cache not available cs5 area: cache not available cs6 area: cache not available cs7 area: cache not available data cache setting of csn area (e) settings of each csn area csn area addresses banks vdcszn signal vsb data bus endian format cache setting size (bits) instruction data 0 0000000h to 03fffffh 0, 1 vdcsz0 32 little endian no no 1 0800000h to 0ffffffh 4, 5 vdcsz1 32 little endian yes no 2 0400000h to 07fffffh 2, 3 vdcsz2 8 little endian no yes 3 1000000h to 1ffffffh 6, 7 vdcsz3 8 big endian no no 4 2000000h to 2ffffffh 8, 9 vdcsz4 16 little endian no no 5 3e00000h to 3ffffffh 15 vdcsz5 16 little endian no no 6 3000000h to 39fffffh 10 to 12 vdcsz6 32 little endian no no 7 3a00000h to 3dfffffh 13, 14 vdcsz7 32 big endian no no
chapter 4 bcu preliminary user?s manual a13971ej7v0um 90 figure 4-12. bpc, bsc, bec, bhc register setting example (3/3) (f) memory map bank 0 01fffffh 0200000h 0000000h bank 1 03fffffh 0400000h bank 2 05fffffh 0600000h bank 3 07fffffh 0800000h bank 4 0bfffffh 0c00000h bank 5 0ffffffh 1000000h bank 6 17fffffh 1800000h bank 7 1ffffffh 2000000h bank 9 2ffffffh 3000000h 33fffffh 3400000h bank 11 37fffffh 3800000h bank 12 39fffffh 3a00000h bank 13 3bfffffh 3c00000h bank 14 3dfffffh 3e00000h bank 15 3ffffffh bank 10 programmable peripheral i/o area (12 kb) 2402fffh 2400000h bank 8 27fffffh 2800000h cs0 area cs2 area cs1 area cs3 area cs4 area cs6 area cs7 area cs5 area
chapter 4 bcu preliminary user?s manual a13971ej7v0um 91 4.9 data transfer using vsb 4.9.1 data transfer example this section uses the circuit shown in figure 4-13 to explain the procedure for transferring data between bus masters and bus slaves connected to the vsb. figure 4-13. example of data transfer using vsb intc stbc cpu vdselpz vaack vareq vareq0 vaack0 vaack2 <1> <2> vsb npb vdcsz5 to vdcsz0 NB85E <4> <3> bus arbiter NB85E interior (bus master 2) dmac bbr vdcsz7 user logic 1 (bus slave 2) bcu memory controller (memc) (bus slave 0) user logic 0 (bus slave 1) vdcsz6 external circuit (bus master 1) tic (bus master 0) lock <1> the NB85E grants bus control (bus access right) to only one bus master according to the on-chip bus arbiter (refer to 4.9.5 bus master transition for detail). the bus arbiter arbitrates the bus access right according to the following prioritization. tic (bus master 0) > external circuit (bus master 1) > NB85E interior (bus master 2) for example, if a bus access right request (vareq) is generated from the tic or an external circuit when the NB85E interior is operating as the bus master, the NB85E interior releases the bus. in the figure shown above, the NB85E interior (bus master 2) receives an acknowledge signal (vaack2: internal signal) from the bus arbiter and has the bus access right (a bus access right request signal is always being output from the NB85E interior to the bus arbiter). <2> bus master 2, which has the bus access right, begins the data transfer to the vsb. <3> the bcu selects the bus slave by generating a chip select signal (vdcszn) corresponding to each bank of the data area according to the programmable chip select function (n = 7 to 0). in the figure shown above, memc (bus slave 0) is selected by the vdcsz5 to vdcsz0 signals. <4> the selected bus slave 0 returns a transfer response to bus master 2, and the data transfer begins.
chapter 4 bcu preliminary user?s manual a13971ej7v0um 92 4.9.2 control signals the bus master that has the bus access right outputs the following types of control signals to indicate the contents of the transfer that is currently being executed. (1) transfer type when the transfer begins, the bus master outputs the vbttyp1 and vbttyp0 signals to indicate the transfer type. table 4-1. vbttyp1 and vbttyp0 signals vbttyp1 vbttyp0 transfer type l l address-only transfer (transfer in which no data processing is performed) h l non-sequential transfer (single transfer or burst transfer) h h sequential transfer (transfer in which the address that is currently being transferred is related to the address for the previous transfer) l h (reserved for future function expansion) remark l: low-level h: high-level (2) bus cycle type the bus master indicates the current bus cycle status according to the vbctyp2 to vbctyp0 signals. table 4-2. vbctyp2 to vbctyp0 signals vbctyp2 vbctyp1 vbctyp0 bus cycle status lllopc ode fetch l l h data access lhl misalign access note l h h read modify write access h l l opcode fetch of jump address due to branch instruction h h l dma 2-cycle transfer hhhdma flyby transfer h l h (reserved for future function expansion) note only output when a high level is input to the ifimaen pin (misalign access enabled). remark l: low-level h: high-level (3) byte enable the bus master uses the vbbenz3 to vbbenz0 signals to indicate the byte data among the data obtained by quartering the data bus (vbd31 to vbd0) into byte units.
chapter 4 bcu preliminary user?s manual a13971ej7v0um 93 table 4-3. vbbenz3 to vbbenz0 signals active (low-level output) signal enabled byte data vbbenz0 vbd7 to vbd0 vbbenz1 vbd15 to vbd8 vbbenz2 vbd23 to vbd16 vbbenz3 vbd31 to vbd24 (4) transfer size the bus master uses the vbsize1 and vbsize0 signals to indicate the transfer size. table 4-4. vbsize1 and vbsize0 signals vbsize1 vbsize0 explanation l l byte (8 bits) l h halfword (16 bits) h l word (32 bits) h h (reserved for future function expansion) remark l: low-level h: high-level (5) sequential status the bus master uses the vbseq2 to vbseq0 signals to indicate the ?burst transfer length? when a burst transfer starts, to indicate ?continuous? during a burst transfer, and to indicate ?single transfer? at the end of the burst transfer. table 4-5. vbseq2 to vbseq0 signals vbseq2 vbseq1 vbseq0 sequential status lllsingle transfer l l h continuous (indicates that the next transfer address is related to the current transfer address) note l h l continuous 4 times (burst transfer length: 4) l h h continuous 8 times (burst transfer length: 8) h l l continuous 16 times (burst transfer length: 16) h l h continuous 32 times (burst transfer length: 32) h h l continuous 64 times (burst transfer length: 64) hhhconti nuous 128 times (burst transfer length: 128) note this is output for continuous 2 times and throughout continuous 4, 8, 16, 32, 64, and 128 times. remark l: low-level h: high-level (6) transfer status the transfer status is indicated by the vbwait, vbahld, and vblast signals, which are output from the bus slave. these signals become effective only while the vbclk signal is low level.
chapter 4 bcu preliminary user?s manual a13971ej7v0um 94 table 4-6. vbwait, vbahld, and vblast signals vbwait vbahld vblast explanation lllstatus w hen the current transfer is completed (ready status) l l h last response (burst transfer last response status) h l l wait response (wait status) h h l maintains address and control signal (address hold status) other than the above (reserved for future function expansion) remark l: low-level h: high-level caution once the vbahld signal becomes active (h), hold the active level until the vbwait signal becomes inactive (l). it is not possible to return to the wait state from the address hold state during a bus cycle. (7) transfer direction the bus master uses the vbwrite signal to indicate the transfer direction. this signal is high level when writing. 4.9.3 read/write timing (1) read timing read data is output from the bus slave side in synchronization with the rising edge of the vbclk signal immediately after the end of address output to the bus slave. following this, the bus master fetches (samples) the data in synchronization with the next falling edge of the vbclk signal. however, if the vbahld signal has been input at an active level (high level), the bus slave outputs data in synchronization with the rising edge of the vbclk signal immediately after the active-level vbahld was input, and the bus master fetches (samples) the data in synchronization with the next falling edge of the vbclk signal. (2) write timing write data is output from the bus master in synchronization with the rising edge of the vbclk signal one clock after the address is output to the bus slave. the following pages show the read/write timing of the bus master and slaves connected to the vsb. the diagrams show the timing seen from the NB85E side when the NB85E has bus mastership. remarks 1. the levels of the broken-line portions indicate the undefined state (weak unknown) entered when the NB85E internal bus holder is driving. 2. the o marks indicate the sampling timing. 3. adrs.n: arbitrary address output from the vba27 to vba0 pins data.n: data output to adrs.n vbwait ( in p ut ) vbahld ( in p ut ) vbwait ( in p ut ) vbahld ( in p ut )
chapter 4 bcu preliminary user?s manual a13971ej7v0um 95 figure 4-14. read/write timing of bus slave connected to vsb (1/12) (a) 32-bit bus (single transfer, no waits) vbttyp1,vbttyp0 (output) adrs.0 vblock (output) vba27 to vba0 (output) vbwrite (output) read write idle vbclk (input) vbstz (output) vbwait (input) vbahld (input) vblast (input) data.0 vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbseq2 to vbseq0 (output) vbsize1,vbsize0 (output) vbbstr (output) vbdc (output) vdcsz7 to vdcsz0 (output) vdselpz (output) ffh (0,0) (0,0,0,0) l h l l l xxh (1,0) (1,0) adrs.1 adrs.3 adrs.2 adrs.5 adrs.4 adrs.7 adrs.6 adrs.9 adrs.8 (0,0,0,0) xxh data.1 data.2 data.3 data.4 data.5 data.6 data.7 data.8 data.9 l idle (0,0) (0,0,1) (0,0,0) (1,0) ffh undefined (1,1,1,1) (1,1,1,1) undefined undefined undefined
chapter 4 bcu preliminary user?s manual a13971ej7v0um 96 figure 4-14. read/write timing of bus slave connected to vsb (2/12) (b) 32-bit bus (single transfer, 1 wait inserted) vbttyp1,vbttyp0 (output) vblock (output) vba27 to vba0 (output) vbwrite (output) read write idle vbstz (output) vbwait (input) vbahld (input) vblast (input) data.0 vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbseq2 to vbseq0 (output) vbsize1,vbsize0 (output) vbbstr (output) vbdc (output) vdcsz7 to vdcsz0 (output) vdselpz (output) ffh (0,0) l h l l l xxh (1,0) (0,0,0,0) xxh (1,1) (1,0) (1,1) (1,0) (1,1) (1,0) (1,1) (1,0) (1,1) (1,0) (1,1) (1,0) (1,1) (1,0) (1,1) adrs.0 idle (0,0) adrs.1 adrs.2 adrs.3 adrs.4 adrs.5 adrs.6 adrs.7 (0,0,0,0) (0,0,1) (0,0,0) (1,0) data.1 data.2 data.3 data.4 data.5 data.6 data.7 vbclk (input) ffh (1,1,1,1) (1,1,1,1) undefined undefined
chapter 4 bcu preliminary user?s manual a13971ej7v0um 97 figure 4-14. read/write timing of bus slave connected to vsb (3/12) (c) 32-bit bus (single transfer, 2 waits inserted) vbttyp1,vbttyp0 (output) vblock (output) vba27 to vba0 (output) vbwrite (output) read write idle vbstz (output) vbwait (input) vbahld (input) vblast (input) data.0 vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbseq2 to vbseq0 (output) vbsize1,vbsize0 (output) vbbstr (output) vbdc (output) vdcsz7 to vdcsz0 (output) vdselpz (output) ffh (0,0) l h l l l xxh (1,0) (0,0,0,0) xxh (1,0) adrs.0 idle (0,0) adrs.1 adrs.2 adrs.3 adrs.4 (0,0,1) (0,0,0) (1,0) data.1 data.2 data.3 data.4 vbclk (input) (1,1) (1,0) (1,1) (1,0) (1,1) (1,1) (1,0) (1,1) ffh (0,0,0,0) (1,1,1,1) (1,1,1,1) undefined undefined
chapter 4 bcu preliminary user?s manual a13971ej7v0um 98 figure 4-14. read/write timing of bus slave connected to vsb (4/12) (d) 32-bit bus (single transfer, 2 waits inserted, with address hold) vbttyp1,vbttyp0 (output) vblock (output) vba27 to vba0 (output) vbwrite (output) read idle vbstz (output) vbwait (input) vbahld (input) vblast (input) data.0 vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbseq2 to vbseq0 (output) vbsize1,vbsize0 (output) vbbstr (output) vbdc (output) vdcsz7 to vdcsz0 (output) vdselpz (output) (0,0) l h l l xxh (1,0) adrs.0 adrs.1 adrs.2 data.1 vbclk (input) (1,1) (1,0) (1,1) (1,0) (1,1) ffh (0,0,1) (0,0,0) (1,0) data.2 l (0,0,0,0) (1,1,1,1) undefined
chapter 4 bcu preliminary user?s manual a13971ej7v0um 99 figure 4-14. read/write timing of bus slave connected to vsb (5/12) (e) 32-bit bus (4-word sequential transfer, data access) vbttyp1,vbttyp0 (output) adrs.0 vblock (output) vba27 to vba0 (output) vbwrite (output) read write idle vbclk (input) vbstz (output) vbwait (input) vbahld (input) vblast (input) data.0 vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbseq2 to vbseq0 (output) vbsize1,vbsize0 (output) vbbstr (output) vbdc (output) vdcsz7 to vdcsz0 (output) vdselpz (output) ffh (0,0) (0,0,0,0) h l l xxh (1,1) (1,1) adrs.1 adrs.3 adrs.2 adrs.5 adrs.4 adrs.7 adrs.6 (0,0,0,0) xxh data.1 data.2 data.3 idle (0,0) (0,0,1) (0,1,0) (1,0) ffh (1,0) (1,0) (0,0,1) (0,1,0) (0,0,1) data.4 l data.5 data.6 data.7 (1,1,1,1) (1,1,1,1) undefined (0,0,0) (0,0,0) undefined undefined undefined
chapter 4 bcu preliminary user?s manual a13971ej7v0um 100 figure 4-14. read/write timing of bus slave connected to vsb (6/12) (f) 16-bit bus (4-word sequential transfer, data access) vbttyp1,vbttyp0 (output) vblock (output) vba27 to vba0 (output) vbwrite (output) read write vbstz (output) vbwait (input) vbahld (input) vblast (input) data.0 vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbseq2 to vbseq0 (output) vbsize1,vbsize0 (output) vbbstr (output) vbdc (output) vdcsz7 to vdcsz0 (output) vdselpz (output) (1,1,0,0) h l l xxh (1,1) xxh data.2 (0,0,1) (0,1,1) (1,0) (1,0) (0,0,1) (0,0,0) (0,1,1) (0,0,1) (0,0,0) l data.9 data.11 data.12 idle ffh (0,0) (1,1,1,1) undefined idle ffh (0,0) (1,1,1,1) undefined data.7 vbclk (input) (1,1) adrs.0 adrs.8 (1,1,0,0) data.3 data.4 data.5 data.6 data.10 data.13 data.14 data.15 word transfer word transfer word transfer word transfer word transfer word transfer word transfer word transfer (1,0) adrs.15 adrs.10 adrs.12 adrs.11 adrs.9 adrs.13 adrs.14 adrs.1 adrs.3 adrs.2 adrs.4 adrs.6 adrs.5 adrs.7 data.1 data.8 (1,1,0,0) (1,1,0,0) (1,1,0,0) (1,1,0,0) (1,1,0,0) (1,1,0,0) (1,1,0,0) (1,1,0,0) (1,1,0,0) (1,1,0,0) (1,1,0,0) (1,1,0,0) (1,1,0,0) (1,1,0,0) undefined undefined
chapter 4 bcu preliminary user?s manual a13971ej7v0um 101 figure 4-14. read/write timing of bus slave connected to vsb (7/12) (g) 8-bit bus (4-byte sequential transfer, external rom fetch) vbttyp1,vbttyp0 (output) adrs.0 vblock (output) vba27 to vba0 (output) vbwrite (output) read read idle vbclk (input) vbstz (output) vbwait (input) vbahld (input) vblast (input) data.0 vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbseq2 to vbseq0 (output) vbsize1,vbsize0 (output) vbbstr (output) vbdc (output) vdcsz7 to vdcsz0 (output) vdselpz (output) ffh (0,0) (1,1,1,0) h l l xxh (1,1) (1,1) adrs.1 adrs.3 adrs.2 adrs.5 adrs.4 adrs.7 adrs.6 (1,1,1,0) xxh data.1 data.2 data.3 idle (0,0) (0,0,0) (0,1,0) (1,0) ffh undefined (1,0) (1,0) l (0,0,1) (0,1,0) (0,0,1) data.4 data.5 data.6 data.7 (1,1,1,1) (1,1,1,1) (0,0,0) (0,0,0) undefined undefined undefined
chapter 4 bcu preliminary user?s manual a13971ej7v0um 102 figure 4-14. read/write timing of bus slave connected to vsb (8/12) (h) 32-bit bus (little-endian, word/halfword/byte transfer) vbttyp1,vbttyp0 (output) vblock (output) vba27 to vba0 (output) vbwrite (output) read write vbstz (output) vbwait (input) vbahld (input) vblast (input) data.0 vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbseq2 to vbseq0 (output) vbsize1,vbsize0 (output) vbbstr (output) vbdc (output) vdcsz7 to vdcsz0 (output) vdselpz (output) h l l xxh data.1 data.2 (0,0,1) (1,0) (0,0,0) l idle ffh (0,0) vbclk (input) (1,0) data.3 data.4 data.5 data.6 undefined word transfer byte transfer word transfer byte transfer idle (0,0) l (1,0) (0,1) (0,0) (1,0) (0,1) (0,0) xxh ffh l halfword transfer halfword transfer (1,1,1,1) adrs.10 adrs.12 adrs.11 adrs.9 adrs.13 adrs.8 adrs.7 (0,0,1,1) (1,1,1,0) (1,1,0,1) (1,0,1,1) (0,1,1,1) (0,0,0,0) (1,1,0,0) adrs.1 adrs.3 adrs.2 adrs.0 adrs.4 adrs.6 adrs.5 (1,1,1,1) (0,0,1,1) (1,1,1,0) (1,1,0,1) (1,0,1,1) (0,1,1,1) (0,0,0,0) (1,1,0,0) data.7 data.8 data.9 data.10 data.11 data.12 data.13 undefined undefined undefined
chapter 4 bcu preliminary user?s manual a13971ej7v0um 103 figure 4-14. read/write timing of bus slave connected to vsb (9/12) (i) 32-bit bus (big-endian, word/halfword/byte transfer) vbttyp1,vbttyp0 (output) vblock (output) vba27 to vba0 (output) vbwrite (output) read write vbstz (output) vbwait (input) vbahld (input) vblast (input) data.0 vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbseq2 to vbseq0 (output) vbsize1,vbsize0 (output) vbbstr (output) vbdc (output) vdcsz7 to vdcsz0 (output) vdselpz (output) h l l xxh data.2 (0,0,1) (1,0) (0,0,0) l idle ffh (0,0) vbclk (input) (1,0) data.3 data.4 data.5 data.6 undefined word transfer byte transfer word transfer byte transfer idle (0,0) l (1,0) (0,1) (0,0) (1,0) (0,1) (0,0) xxh ffh l halfword transfer halfword transfer adrs.10 adrs.12 adrs.11 adrs.9 adrs.13 adrs.8 adrs.7 (0,0,0,0) (1,1,0,0) (0,1,1,1) (1,0,1,1) (1,1,0,1) (1,1,1,0) (0,0,1,1) (1,1,1,1) adrs.1 adrs.3 adrs.2 adrs.0 adrs.4 adrs.6 adrs.5 (1,1,0,0) (0,1,1,1) (1,0,1,1) (1,1,0,1) (1,1,1,0) (0,0,0,0) (0,0,1,1) data.1 data.7 data.8 data.9 data.10 data.11 data.12 data.13 (1,1,1,1) undefined undefined undefined
chapter 4 bcu preliminary user?s manual a13971ej7v0um 104 figure 4-14. read/write timing of bus slave connected to vsb (10/12) (j) 16-bit bus (little-endian, word/halfword/byte transfer) vbttyp1,vbttyp0 (output) vblock (output) vba27 to vba0 (output) vbwrite (output) read write vbstz (output) vbwait (input) vbahld (input) vblast (input) data.0 vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbseq2 to vbseq0 (output) vbsize1,vbsize0 (output) vbbstr (output) vbdc (output) vdcsz7 to vdcsz0 (output) vdselpz (output) h l l adrs.1 adrs.3 adrs.2 data.1 data.2 (0,0,0) l idle ffh (0,0) undefined vbclk (input) adrs.0 adrs.4 adrs.6 adrs.5 data.3 data.4 data.5 data.6 word transfer byte transfer word transfer byte transfer idle undefined (0,1) l halfword transfer halfword transfer (0,0,1) (1,1) (1,0) (1,0) (0,0) (1,1) (1,0) adrs.7 (1,1,0,0) (1,1,1,1) (1,1,0,0) (1,1,1,1) (0,0,1) (0,0,0) (0,0,1) (1,0) (0,0) (0,1) (1,0) (0,0) undefined xxh ffh xxh data.7 (1,0) adrs.11 adrs.13 adrs.12 adrs.10 adrs.14 adrs.9 adrs.8 adrs.15 (1,1,1,0) (1,1,0,1) (1,1,1,0) (1,1,0,1) data.8 data.9 data.10 data.11 data.12 data.13 data.14 data.15 (1,1,1,0) (1,1,0,1) (1,1,1,0) (1,1,0,1) undefined
chapter 4 bcu preliminary user?s manual a13971ej7v0um 105 figure 4-14. read/write timing of bus slave connected to vsb (11/12) (k) 16-bit bus (big-endian, word/halfword/byte transfer) vbttyp1,vbttyp0 (output) vblock (output) vba27 to vba0 (output) vbwrite (output) read write vbstz (output) vbwait (input) vbahld (input) vblast (input) data.0 vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbseq2 to vbseq0 (output) vbsize1,vbsize0 (output) vbbstr (output) vbdc (output) vdcsz7 to vdcsz0 (output) vdselpz (output) h l l data.1 data.2 (1,0) (0,0,0) l idle ffh (0,0) undefined vbclk (input) data.3 data.4 data.5 data.6 word transfer byte transfer word transfer byte transfer idle undefined (0,1) l halfword transfer halfword transfer (0,0,1) (1,1) (1,0) (1,0) (0,0) (1,1) (1,0) (1,1,0,0) (1,1,1,1) (1,1,0,0) (1,1,1,1) (0,0,1) (0,0,0) (0,0,1) (1,0) (0,0) (0,1) (1,0) (0,0) undefined xxh ffh xxh data.7 adrs.11 adrs.13 adrs.12 adrs.10 adrs.14 adrs.8 adrs.15 (1,1,0,1) (1,1,1,0) (1,1,0,1) (1,1,1,0) adrs.9 adrs.1 adrs.3 adrs.2 adrs.0 adrs.4 adrs.6 adrs.5 (1,1,0,1) (1,1,1,0) (1,1,0,1) adrs.7 (1,1,1,0) data.8 data.9 data.10 data.11 data.12 data.13 data.14 data.15 undefined
chapter 4 bcu preliminary user?s manual a13971ej7v0um 106 figure 4-14. read/write timing of bus slave connected to vsb (12/12) (l) 8-bit bus (little/big-endian, word/halfword/byte transfer) vbttyp1,vbttyp0 (output) vblock (output) vba27 to vba0 (output) vbwrite (output) read write vbstz (output) vbwait (input) vbahld (input) vblast (input) vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbseq2 to vbseq0 (output) vbsize1,vbsize0 (output) vbbstr (output) vbdc (output) vdcsz7 to vdcsz0 (output) vdselpz (output) h l l adrs.1 adrs.3 adrs.2 (1,0) (0,0,1) l idle ffh (0,0) undefined adrs.0 adrs.4 adrs.6 adrs.5 word transfer byte transfer idle undefined (0,1) l halfword transfer (0,0,1) (1,1) (1,0) adrs.7 (1,1,1,0) (1,1,1,1) (1,1,1,0) (1,1,1,1) (0,1,0) (1,0) (0,0) undefined xxh ffh xxh (1,0) (1,1) (1,0) (1,1) (1,0) (1,1) (1,0) (1,1) (1,0) (0,0) adrs.8 adrs.9 (0,0,0) (0,0,1) (0,0,0) (0,0,1) (0,0,0) (0,1,0) (0,0,1) (0,0,0) (0,0,1) (0,0,0) (0,1) (1,0) (0,0) data.8 data.9 byte transfer halfword transfer word transfer vbclk (input) adrs.11 adrs.13 adrs.12 adrs.10 adrs.14 adrs.15 adrs.16 adrs.17 data.0 data.1 data.2 data.3 data.4 data.5 data.6 data.7 data.12 data.13 data.16 data.17 data.10 data.11 data.14 data.15 undefined
chapter 4 bcu preliminary user?s manual a13971ej7v0um 107 4.9.4 reset timing the reset timing of when a low level is input to the ifirome pin (the connected rom is used as external memory (via the vsb)) is shown below. caution be sure to input the vbclk signal continuously during the reset period (the period when dcresz is low level). figure 4-15. reset timing vbttyp1,vbttyp0 (output) vblock (output) vba27 to vba0 (output) vbwrite (output) vbstz (output) vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbseq2 to vbseq0 (output) vbsize1,vbsize0 (output) vdcsz7 to vdcsz0 (output) vdselpz (output) (0, 0) dcresz (input) (0, 0) (1, 0) l a drs.0 a drs.1 l (0,0,0,0) (1,0,0) (0,0,0) (0,0,0) (1, 0) ffh ffh feh feh feh h data.1 l ifirome (input) (1,1,1,1) (0, 0) (1, 0) (1, 0) data.0 undefined (0,0,0,0) a drs.2 (1,1,1,1) (0,0,0,0) (1,0,0) undefined undefined undefined undefined vbclk (input) remarks 1. the levels of dotted-line portions indicate the undefined state (weak unknown) entered when the NB85E internal bus holder is driving. 2 . adrs.n: arbitrary address output from the vba27 to vba0 pins data.n: data of adrs.n
chapter 4 bcu preliminary user?s manual a13971ej7v0um 108 4.9.5 bus master transition (1) bus priority there are five kinds of external bus cycles as shown below. bus hold has the highest priority, followed by refresh cycle, dma cycle, operand data access, and instruction fetch in that order. priority external bus cycle bus master bus hold external device refresh cycle sdram controller dma cycle dma controller operand data access cpu high low instruction fetch cpu (2) NB85E external master device <1> a vsb access right request signal (vareq) is input to the NB85E from the external master device. <2> the NB85E internal bus arbiter enters a state whereby it is waiting for a ready response from the slave device. <3> when execution of the current transfer is complete, the slave device sends the ready response. <4> the vbttyp1 and vbttyp0 signals of the NB85E indicate an address-only transfer, and the NB85E?s vblock, vdcsz7 to vdcsz0, and vdselpz signals are consequently ignored. <5> the NB85E sends an acknowledge signal for the vareq signal (vaack) and a ready response to the external master device. the external master device inactivates the vblock, vdcszn (n = 7 to 0), and vdselpz signals. <6> the external bus master starts transferring data via the vsb. remark the ready response is when the vbwait, vbahld, and vblast signals are all in a low-level state.
chapter 4 bcu preliminary user?s manual a13971ej7v0um 109 figure 4-16. bus arbitration timing (NB85E external master device) vbttyp1, vbttyp0 (external) vba27 to vba0 (external) bus master: NB85E bus master: external master device vbclk vbwait vbahld vblast (1,0) l l vareq vaack vblock (external) hi-z hi-z adrs.2 adrs.3 hi-z vbwrite, vbbenz3 to vbbenz0, vbctyp2 to vbctyp0, vbseq2 to vbseq0, vbsize1, vbsize0, vbstz, vbbstr, vbdc (external) ctrl.2 ctrl.3 hi-z vdcsz7 to vdcsz0 (external) csz.2 csz.3 hi-z hi-z vbd31 to vbd0 (external) data.2 vblock (NB85E) vbttyp1, vbttyp0 (NB85E) hi-z vdselpz (external) (1,1) (0,0) vba27 to vba0 (NB85E) adrs.1 hi-z vbwrite, vbbenz3 to vbbenz0, vbctyp2 to vbctyp0, vbseq2 to vbseq0, vbsize1, vbsize0, vbstz, vbbstr, vbdc (NB85E) ctrl.1 hi-z csz.1 hi-z vdcsz7 to vdcsz0 (NB85E) ffh hi-z vdselpz (NB85E) hi-z vbd31 to vbd0 (NB85E) data.0 <1> <2> <3> <4> <5> <6> data.1 hi-z hi-z hi-z hi-z hi-z ffh remark the levels of dotted-line portions of the vbttyp1, vbttyp0, vbwait, vbahld, and vblast signals indicate the undefined state (weak unknown) entered when the NB85E internal bus holder is driving.
chapter 4 bcu preliminary user?s manual a13971ej7v0um 110 (3) external bus master NB85E <1> the external master device inactivates the vsb access right request signal (vareq). <2> the bus arbiter enters a state whereby it is waiting for a ready response form the slave device. <3> when execution of the current transfer is complete, the slave device sends the ready response. <4> the vbttyp1 and vbttyp0 signals of the external master device indicate an address-only transfer, and the external master device?s vblock, vdcsz7 to vdcsz0, and vdselpz signals are consequently ignored. <5> the NB85E inactivates the acknowledge signal for the vareq signal (vaack) and sends a ready response. the NB85E also inactivates the vblock, vdcszn (n = 7 to 0), and vdselpz signals. <6> the NB85E starts transferring data via the vsb. remark the ready response is when the vbwait, vbahld, and vblast signals are all in a low-level state.
chapter 4 bcu preliminary user?s manual a13971ej7v0um 111 figure 4-17. bus arbitration timing (external master device NB85E) bus master: external master device bus master: NB85E vbclk vbwait vbahld vblast l l vareq vaack vbttyp1, vbttyp0 (NB85E) vba27 to vba0 (NB85E) (1,0) vblock (NB85E) hi-z hi-z adrs.2 adrs.3 hi-z vbwrite, vbbenz3 to vbbenz0, vbctyp2 to vbctyp0, vbseq2 to vbseq0, vbsize1, vbsize0, vbstz, vbbstr, vbdc (NB85E) ctrl.2 ctrl.3 hi-z vdcsz7 to vdcsz0 (NB85E) csz.2 csz.3 hi-z hi-z vbd31 to vbd0 (NB85E) data.2 hi-z vdselpz (NB85E) <1> <2> <3> <4> <5> <6> hi-z vblock (external) vbttyp1, vbttyp0 (external) (1,1) (0,0) hi-z vba27 to vba0 (external) adrs.1 hi-z vbwrite, vbbenz3 to vbbenz0, vbctyp2 to vbctyp0, vbseq2 to vbseq0, vbsize1, vbsize0, vbstz, vbbstr, vbdc (external) ctrl.1 hi-z csz.1 hi-z vdcsz7 to vdcsz0 (external) ffh hi-z vdselpz (external) hi-z vbd31 to vbd0 (external) data.0 data.1 hi-z hi-z ffh hi-z remark the levels of dotted-line portions of the vbttyp1, vbttyp0, vbwait, vbahld, and vblast signals indicate the undefined state (weak unknown) entered when the NB85E internal bus holder is driving.
chapter 4 bcu preliminary user?s manual a13971ej7v0um 112 4.9.6 misalign access timing the vsb access timing when misalign access is enabled (when a high level is input to the ifimaen pin) is shown below. figure 4-18. misalign access timing (1/2) (a) timing for access to even addresses (writing the 32-bit data ?12345678h? to address ?200002h?) vbttyp1,vbttyp0 (output) vblock (output) vba27 to vba0 (output) vbstz (output) vbctyp2 to vbctyp0 (output) vbseq2 to vbseq0 (output) vbsize1,vbsize0 (output) vdcsz7 to vdcsz0 (output) vbclk (input) 200002h 200004h vbwrite (output) h (0,1,0) (0,0,0) (0,1) vbd31 to vbd0 (i/o) vbwait (input) vbahld (input) vblast (input) l l 5678xxxxh xxxx1234h halfword write halfword write (1, 0) (1, 1) (1, 0) (1, 1) (0, 0, 1, 1) (1, 1, 0, 0) vbbenz3 to vbbenz0 (output) remark the levels of the broken-line portions indicate the undefined state (weak unknown) entered when the NB85E internal bus holder is driving.
chapter 4 bcu preliminary user?s manual a13971ej7v0um 113 figure 4-18. misalign access timing (2/2) (b) timing for access to odd addresses (writing the 32-bit data ?12345678h? to address ?200003h?) (1,0) (0,1,1,1) (1,1) (1,0) (1,1) 200003h 200004h h (1,1,0,0) (0,1,0) (0,0,0) l l (1,0) (1,1) 200006h (1,0,1,1) byte write halfword write byte write (0,1) 78xxxxxxh xxxx3456h xx12xxxxh (0,0) (0,0) vbclk (input) vbttyp1,vbttyp0 (output) vblock (output) vba27 to vba0 (output) vbwrite (output) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbseq2 to vbseq0 (output) vbsize1,vbsize0 (output) vbstz (output) vdcsz7 to vdcsz0 (output) vbd31 to vbd0 (i/o) vbwait (input) vbahld (i nput) vblast (input) remark the levels of the broken-line portions indicate the undefined state (weak unknown) entered when the NB85E internal bus holder is driving.
preliminary user?s manual a13971ej7v0um 114 chapter 5 bbr the bus bridge (bbr) converts signals that are passed between the vsb and npb. the bbr sets up the following functions for peripheral macros that are connected to the npb. ? wait insertion function ? retry function figure 5-1. npb connection overview bcu bbr peripheral macro (1) vsb (high speed) NB85E npb (low speed) peripheral macro (2) peripheral macro (3) peripheral macro (4)
chapter 5 bbr preliminary user's manual a13971ej7v0um 115 the following figure shows a connection example connecting the NB85E and peripheral macros that are connected to the npb. figure 5-2. NB85E and peripheral macro connection example bbr vpa13 to vpa0 vpwrite address decoder vpd15 to vpd0 vpstb vpubenz vplock vpretr vpcs vpdw15 to vpdw0 vpdr15 to vpdr0 peripheral macro (1) vpcs vpdw15 to vpdw0 vpdr15 to vpdr0 peripheral macro (2) NB85E bus holder (1) bus holder (16) ? vpan note to vpa0 vpwrite vpstb vpubenz vplock vpretr vpan note to vpa0 vpwrite vpstb vpubenz vplock vpretr vpdact vpresz vpresz vpresz note the value of n differs according to the type of peripheral macro that is connected to the npb.
chapter 5 bbr preliminary user's manual a13971ej7v0um 116 5.1 programmable peripheral i/o area the NB85E has a 4 kb peripheral i/o area that is allocated in advance in the address space and a 12 kb programmable peripheral i/o area that can be allocated at arbitrary addresses according to register settings (see 4.4 programmable peripheral i/o area selection function ). if the peripheral i/o area or programmable peripheral i/o area in the memory map shown in figure 5-3 is accessed, the npb becomes active. the programmable peripheral i/o area is set by the peripheral i/o area select control register (bpc). figure 5-3. peripheral i/o area and programmable peripheral i/o area (a) 64 mb mode (b) 256 mb mode note see figure 3-8 data area (256 mb mode) . remarks 1. xxx: setting according to the pa13 to pa02 bits of the bpc register yy: setting according to the pa01 and pa00 bits of the bpc register 2. since the areas indicated by ?same area? are linked, if data is written in one area, data having the same contents is also written in the other area. (n = yy11b) peripheral i/o area (4 kb) (4 kb) programmable peripheral i/o area (12 kb) fffffffh ffff000h fffefffh 0000000h xxxnfffh xxxm000h 3fff000h 3ffefffh 3ffffffh 3fff000h 3ffefffh xxxnfffh xxxm000h 0000000h same area (m = yy00b) same area same area note peripheral i/o area (4 kb) (4 kb) programmable peripheral i/o area (12 kb) (ram area) (n = yy11b) (m = yy00b)
chapter 5 bbr preliminary user's manual a13971ej7v0um 117 figure 5-4. peripheral i/o area select control register (bpc) 1514131211109876543210 bpc pa 15 0 pa 13 pa 12 pa 11 pa 10 pa 09 pa 08 pa 07 pa 06 pa 05 pa 04 pa 03 pa 02 pa 01 pa 00 address fffff064h after reset 0000h bit position bit name function 15 pa15 sets whether or not the programmable peripheral i/o area can be accessed. 0: it cannot be accessed 1: it can be accessed 13 to 0 pa13 to pa00 specifies bit 27 to bit 14 of the starting address of the programmable peripheral i/o area. (the other bits are fixed at zero.) caution always set bit 14 to 0. if it is set to 1, operation is not guaranteed. cautions 1. in 64 mb mode, if the programmable peripheral i/o area overlaps the following areas, the programmable peripheral i/o area becomes ineffective. ? ? ? ? peripheral i/o area ? ? ? ? rom area ? ? ? ? ram area 2. in 256 mb mode, if the programmable peripheral i/o area overlaps the following areas, the programmable peripheral i/o area becomes ineffective. ? ? ? ? peripheral i/o area ? ? ? ? rom area ? ? ? ? ram area ? ? ? ? the area that is the same as the ram area and that is located at address 3ffefffh and below (see figure 3-8 data area (256 mb mode)) 3. if no peripheral macros are connected to the npb, no programmable peripheral i/o area need be set (set the bpc register to its after-reset value). 4. the programmable peripheral i/o area address setting is enabled only once. do not change addresses in the middle of a program. figure 5-5 shows a bpc register setting example and the memory map after the setting is made.
chapter 5 bbr preliminary user's manual a13971ej7v0um 118 figure 5-5. bpc register setting example (a) bpc register setting 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1514131211109876543210 bpc programmable peripheral i/o area: can be accessed programmable peripheral i/o area starting address: 2400000h (b) memory map [64 mb mode] [256 mb mode] bank 0 01fffffh 0200000h 0000000h bank 1 03fffffh 0400000h bank 2 05fffffh 0600000h bank 3 07fffffh 0800000h 3ffffffh 4000000h 7ffffffh 8000000h bffffffh c000000h f7fffffh f800000h bank 12 f9fffffh fa00000h bank 13 fbfffffh fc00000h bank 14 fdfffffh fe00000h bank 15 fffffffh area 2 area 3 programmable peripheral i/o area 2402fffh 2400000h area 1 area 0 bank 0 01fffffh 0200000h 0000000h bank 1 03fffffh 0400000h bank 2 05fffffh 0600000h bank 3 07fffffh 0800000h bank 4 0bfffffh 0c00000h bank 5 0ffffffh 1000000h bank 6 17fffffh 1800000h bank 7 1ffffffh 2000000h 27fffffh 2800000h bank 9 2ffffffh 3000000h 33fffffh 3400000h bank 11 37fffffh 3800000h bank 12 39fffffh 3a00000h bank 13 3bfffffh 3c00000h bank 14 3dfffffh 3e00000h bank 15 3ffffffh bank 10 programmable peripheral i/o area 2402fffh 2400000h bank 8
chapter 5 bbr preliminary user's manual a13971ej7v0um 119 5.2 wait insertion function the bbr is equipped with a wait insertion function for connection with low-speed peripheral macros that are connected to the npb. the npb strobe wait control register (vswc) is used to set up this function. the vswc register sets the setup wait length and vpstb wait length (see figure 5-6 ). the number of waits can be set in the range from 0 to 7 clocks based on the internal system clock (vbclk). figure 5-6. npb strobe wait control register (vswc) (1/2) 76543210 vswc 0 suwl2 suwl1 suwl0 0 vswl2 vswl1 vswl0 address fffff06eh after reset 77h bit position bit name function 6 to 4 suwl2 to suwl0 sets the setup wait length. suwl2 suwl1 suwl0 setup wait length 0 000 (no waits) 0 011 t clk 0 102 t clk 0 113 t clk 1 004 t clk 1 015 t clk 1 106 t clk 1 117 t clk remark t clk : internal system clock (vbclk) cycle
chapter 5 bbr preliminary user's manual a13971ej7v0um 120 figure 5-6. npb strobe wait control register (vswc) (2/2) bit position bit name function 2 to 0 sets the vpstb wait length. vswl2 vswl1 vswl0 vpstb wait length 0 000 (no waits) 0 011 t clk 0 102 t clk 0 113 t clk 1 004 t clk 1 015 t clk 1 106 t clk 1 117 t clk vswl2 to vswl0 remark t clk : internal system clock (vbclk) cycle be sure to set values for the setup wait and vpstb wait lengths at each operation frequency that are the same as or greater than the number of waits shown in table 5-1 below. table 5-1. setting of setup wait, vpstb wait lengths at each operation frequency wait length operation frequency to 25 mhz to 33 mhz to 50 mhz to 66 mhz setup wait length (set using bits suwl2 to suwl0) 1 1 1 1 vpstb wait length (set using bits vswl2 to vswl0) 1 2 4 5 caution these setting values are not guaranteed, so be sure to set the number of waits appropriate to the system after verifying operation. vpstb (output) vpa13 to vpa0 (output) vpstb wait 1 clock 0.5 clock setup wait vbclk (input) 1.5 clock
chapter 5 bbr preliminary user's manual a13971ej7v0um 121 5.3 retry function the retry function, which repeats read or write processing according to a retry request signal (vpretr) from a peripheral macro on the npb, is used in situations such as when the data setup time is insufficient. if a high-level signal is being input to the vpretr and vpdact pins at the falling edge of the vpstb signal, the vpstb signal rises again and the read or write operation is repeated. figure 5-7. retry function vpa13 to vpa0 (output) vpd15 to vpd0 (i/o) address vpstb (output) vpretr (input) vpdact (input) 1clock note 1 data (output) address 1clock note 1 read write vpwrite (output) data (input) data (input) undefined note 2 undefined note 2 undefined note 2 notes 1. this is the same width as one vbclk clock. 2. the undefined state (weak unknown) entered when the NB85E internal bus holder is driving
chapter 5 bbr preliminary user's manual a13971ej7v0um 122 5.4 npb read/write timing figure 5-8. halfword access timing vpa13 to vpa0 (output) address address vpd15 to vpd0 (i/o) write read vpwrite (output) vpstb (output) vpubenz (output) vplock (output) l vpretr (input) data data undefined note undefined note note the undefined state (weak unknown) entered when the NB85E internal bus holder is driving
chapter 5 bbr preliminary user's manual a13971ej7v0um 123 figure 5-9. timing of byte access to odd address vpa13 to vpa0 (output) address address vpd15 to vpd8 (i/o) write read vpwrite (output) vpstb (output) vpubenz (output) vplock (output) l vpretr (input) data vpd7 to vpd0 (i/o) undefined note undefined note data undefined note note the undefined state (weak unknown) entered when the NB85E internal bus holder is driving figure 5-10. timing of byte access to even address vpa13 to vpa0 (output) address address vpd7 to vpd0 (i/o) data write read vpwrite (output) vpstb (output) vpubenz (output) vplock (output) l vpretr (input) vpd15 to vpd8 (i/o) undefined note data undefined note undefined note note the undefined state (weak unknown) entered when the NB85E internal bus holder is driving
chapter 5 bbr preliminary user's manual a13971ej7v0um 124 figure 5-11. read modify write timing note the undefined state (weak unknown) entered when the NB85E internal bus holder is driving remark the vplock signal becomes active during a read operation. figure 5-12. retry timing (write) remark if the vpretr and vpdact signals are high level at the falling edge of the vpstb signal, the vpstb signal becomes active, and the write operation is performed again. read write idle vpa13 to vpa0 (output) address vpwrite (output) vpstb (output) vpubenz (output) vplock (output) vpretr (input) vpd15 to vpd0 (i/o) l data data undefined note undefined note undefined note undefined note address vpa13 to vpa0 (output) address vpd15 to vpd0 (i/o) vpwrite (output) vpstb (output) vpubenz (output) vplock (output) vpretr (input) data vpdact (input)
chapter 5 bbr preliminary user's manual a13971ej7v0um 125 figure 5-13. retry timing (read) note the undefined state (weak unknown) entered when the NB85E internal bus holder is driving remark if the vpretr and vpdact signals are high level at the falling edge of the vpstb signal, the vpstb signal becomes active, and the read operation is performed again. vpa13 to vpa0 (output) address vpwrite (output) vpstb (output) vpubenz (output) vplock (output) vpretr (input) vpd15 to vpd0 (i/o) data data undefined note undefined note undefined note vpdact (input)
chapter 5 bbr preliminary user's manual a13971ej7v0um 126 figure 5-14. read/write timing of bus slave connected to npb (1/3) (a) example of timing of write to npb peripheral macro (programmable peripheral i/o area) remark the levels of broken-line portions indicate the undefined state (weak unknown) entered when the NB85E internal bus holder is dr iving. vbttyp1, vbttyp0 (output) vblock (output) vba27 to vba0 (output) vbwrite (output) vbstz (output) vbwait (input) vbahld (input) vblast (input) vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbsize1, vbsize0 (output) vdcsz7 to vdcsz0 (output) vdselpz (output) vpstb (output) vpwrite (output) vpubenz (output) vpd15 to vpd0 (i/o) vpa13 to vpa0 (output) vpretr (input) vbseq2 to vbseq0 (output) (1,1) l (1,1,0,0) vbclk (input) l l h undefined 3800h 3802h 3804h l ffh (1,0) (0,1) (0,0,1) xxxx1234h xxxx5678h xxxx00ffh 2403802h 2403800h 2403804h (1,0) (1,1) (1,0) (1,0) word-data write halfword-data write (1,1) unde- fined (0,0,1) (0,0,0) 1234h 00ffh 5678h undefined undefined undefined
chapter 5 bbr preliminary user's manual a13971ej7v0um 127 figure 5-14. read/write timing of bus slave connected to npb (2/3) (b) example of timing of write/read to/from npb peripheral macro (programmable peripheral i/o area) remark the levels of broken-line portions indicate the undefined state (weak unknown) entered when the NB85E internal bus holder is dr iving. vbttyp1, vbttyp0 (output) vblock (output) vba27 to vba0 (output) vbwrite (output) vbstz (output) vbwait (input) vbahld (input) vblast (input) vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbsize1, vbsize0 (output) vdcsz7 to vdcsz0 (output) vdselpz (output) vpstb (output) vpwrite (output) vpubenz (output) vpd15 to vpd0 (i/o) vpa13 to vpa0 (output) vpretr (input) vbseq2 to vbseq0 (output) (1,1) (0,0,1) vbclk (input) l undefined 3806h 3800h 3802h ffh (0,0,0) xxxx55aah 2403800h 2403806h 2403802h (1,1) (1,1) halfword-data write undefined xxxx5678h undefined xxxx5678h undefined xxxx1234h (1,1,0,0) (0,0,1) (0,0,0) (0,1) 5678h 5678h 1234h word-data read (1,0) 55aah (1,0) (1,0) (1,0) l l undefined undefined undefined undefined
chapter 5 bbr preliminary user's manual a13971ej7v0um 128 figure 5-14. read/write timing of bus slave connected to npb (3/3) (c) example of timing of read from npb peripheral macro (programmable peripheral i/o area) remark the levels of broken-line portions indicate the undefined state (weak unknown) entered when the NB85E internal bus holder is dr iving. vbttyp1, vbttyp0 (output) vblock (output) vba27 to vba0 (output) vbwrite (output) vbstz (output) vbwait (input) vbahld (input) vblast (input) vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbsize1, vbsize0 (output) vdcsz7 to vdcsz0 (output) vdselpz (output) vpstb (output) vpwrite (output) vpubenz (output) vpd15 to vpd0 (i/o) vpa13 to vpa0 (output) vpretr (input) vbseq2 to vbseq0 (output) (1,1) vbclk (input) l l 3804h 3806h ffh (0, 1) (0,0,0) xxxx55aah xxxx00ffh xxxx55aah 2403806h 2403804h (1,1) halfword-data read l undefined xxxx55aah undefined undefined l (0,0,1) (1,1,0,0) undefined 00ffh undefined 55aah undefined 55aah undefined 55aah (1,0) (1,0) l l undefined undefined undefined
preliminary user?s manual a13971ej7v0um 129 chapter 6 stbc the standby control unit (stbc) implements the various power save functions of the NB85E by controlling the external clock generator (cg). 6.1 power save function the power save function has the following three modes. (1) halt mode this mode, which stops the supply of clocks only to the cpu, is set by executing a special-purpose instruction (halt instruction). since the supply of clocks to internal units other than the cpu continues, operation of the NB85E internal peripheral i/o that do not depend on the cpu instruction processing continues. the power consumption of the overall system can be reduced by intermittent operation that is achieved due to a combination of halt mode and normal operation mode. (2) software stop mode this mode, which stops the overall system by stopping the external clock generator, is set by means of a psc register setting. the system enters an ultra-low power consumption state in which only leak current is lost. (3) hardware stop mode this mode, which stops the overall system by stopping the external clock generator, is set by inputting the dcstopz signal. the system enters an ultra-low power consumption state in which only leak current is lost. figure 6-1. power save function state transition diagram normal operation mode hardware stop mode set halt mode halt mode set software stop mode input dcresz, dcnmin, and intm software stop mode (execute halt instruction) (set psc register) input dcresz, dcnmin, and intm input dcstopz (h) and dcresz input dcstopz (l) input dcstopz (l) input dcstopz (l) input dcstopz (h) remarks 1. n = 2 to 0 m = 63 to 0 2. l: low-level input h: high-level input
chapter 6 stbc preliminary user's manual a13971ej7v0um 130 6.2 control registers 6.2.1 power save control register (psc) the psc is an 8-bit register that controls the power save function. if interrupts are permitted according to the nmi2m to nmi0m and intm bit settings, software stop mode can be canceled by an interrupt request (except when interrupt servicing is prohibited by the interrupt mask register (imr0 to imr3)). software stop mode is specified by setting the stp bit. this register can only be written by using a specific procedure so that its settings are not mistakenly overwritten due to erroneous program execution. this register can be read or written in 8-bit or 1-bit units. caution do not set the psc register by transferring data using the dmac. to set this register, always use a store instruction (st or sst) or a bit manipulation instruction (set1, clr1, or not1 instruction). figure 6-2. power save control register (psc) 76543210 psc nmi2m nmi1m nmi0m intm 0 0 stp 0 address fffff1feh after reset 00h bit position bit name function 7nmi2m masks non-maskable interrupt requests (nmi2) from the dcnmi2 pin. note 0: permits nmi2 requests 1: prohibits nmi2 requests 6nmi1m masks non-maskable interrupt requests (nmi1) from the dcnmi1 pin. note 0: permits nmi1 requests 1: prohibits nmi1 requests 5nmi0m masks non-maskable interrupt requests (nmi0) from the dcnmi0 pin. note 0: permits nmi0 requests 1: prohibits nmi0 requests 4intm masks maskable interrupt r equests (int63 to int0) from the int63 to int0 pins. note 0: permits int63 to int0 requests 1: prohibits int63 to int0 requests 1 stp specifies software stop mode. when this bit is set (1), software stop mode is set. when software stop mode is canceled, this bit is automatically cleared (0). note the setting is valid in software stop mode only.
chapter 6 stbc preliminary user's manual a13971ej7v0um 131 cautions 1. if the nmi2m to nmi0m and intm bits are set (1) at the same time as the stp bit, the settings of the nmi2m to nmi0m and intm bits are invalid. therefore, if there are unmasked interrupt requests pending when software stop mode is entered, be sure to set (1) those interrupt request bits (nmi2m to nmi0m and intm) before setting (1) the stp bit. 2. because an interrupt request that occurs while the nmi2m to nmi0m and intm bits are set (1) is invalid (it is not held pending), software stop mode cannot be canceled. use the procedure shown below to set data in the psc register. <1> write the data that is to be set in the psc register to an arbitrary general-purpose register (see 3.2.1 program registers ). <2> use the store instruction (st or sst instruction) to write the contents of the general-purpose register, which had been prepared in step <1>, to the command register (prcmd). <3> use the following instructions to write the contents of the general-purpose register, which had been prepared in step <1>, to the psc register (do this immediately after writing the contents of the general-purpose register in the prcmd register). ? store instruction (st or sst instruction) ? bit manipulation instruction (set1, clr1, or not1 instruction) <4> if the NB85E switches to software stop mode, insert nop instructions (five or more instructions). examples 1. <1> mov 0x02, r11 movea base_address, r0, r20 ; base_address = ffff000h <2> st.b r11, prcmd[r20] ; prcmd = 01fch <3> st.b r11, psc[r20] ; psc = 01feh <4> nop nop nop nop nop 2. <1> mov 0x02, r11 movea 0xf1fch, r0, r20 movea 0xf1feh, r0, r21 <2> st.b r11, 0x0[r20] ; r20 = fffff1fch ( = prcmd) <3> st.b r11, 0x0[r21] ; r21 = fffff1feh ( = psc) <4> nop nop nop nop nop no special procedure is required to read the contents of the psc register.
chapter 6 stbc preliminary user's manual a13971ej7v0um 132 remarks 1. interrupts are not acknowledged for store instructions for the prcmd register. 2. steps <2> and <3> above are assumed to occur consecutively. if another instruction is placed between the instructions described in steps <2> and <3>, then when the interrupt is acknowledged for that instruction, the setting may not be established, causing abnormal operation. 3. although the data written in the prcmd register is dummy data, use the same value (data) as the value of the general-purpose register used for setting data in a specific register (step <3> in the examples above) even when writing to the prcmd register (step <2> in the examples above). this is similar to using a general-purpose register for addressing. 6.2.2 command register (prcmd) the command register (prcmd) is used to set protection for write operations to the psc register so that the application system is not halted unexpectedly due to erroneous program execution. only the first write operation to the psc register is valid after a registration code (arbitrary 8-bit data) is written to the prcmd register. since the register value can be rewritten only by a predetermined procedure, illegal write operations to the psc register are rejected. data can be written in the prcmd register only in 8-bit units. during reading, the value is undefined. caution do not set the prcmd register by transferring data using the dmac. to set this register, always use a store instruction (st or sst). figure 6-3. command register (prcmd) 76543210 prcmdreg7reg6reg5reg4reg3reg2reg1reg0 address fffff1fch after reset undefined bit position bit name function 7 to 0 reg7 to reg0 this is the registration code (arbitrary 8-bit data) used when write accessing the psc register.
chapter 6 stbc preliminary user's manual a13971ej7v0um 133 6.3 halt mode in halt mode, the operation clock of the cpu is stopped. since the supply of clocks to internal units other than the cpu continues, operation continues. the power consumption of the overall system can be reduced by setting the NB85E to halt mode while the cpu is idle. (1) setting and operation status the NB85E is switched to halt mode by the halt instruction. although program execution stops in halt mode, the contents of all registers and of ram immediately before halt mode began are maintained. also, operation continues for all NB85E-internal peripheral i/o that does not depend on cpu instruction processing. caution insert at least five nop instructions after the halt instruction. (2) cancellation of halt mode halt mode is canceled by a non-maskable interrupt request, an unmasked maskable interrupt request, or the input of the dcresz signal. (a) cancellation by interrupt request halt mode is canceled by a non-maskable interrupt request or by an unmasked maskable interrupt request regardless of the priority. the following table shows the operation performed after halt mode is canceled. table 6-1. operation after halt mode is canceled by interrupt request cancellation source interrupt enabled (ei) state interrupt disabled (di) state non-maskable interrupt request branch to handler address maskable interrupt request branch to handler address or execution of next instruction execution of next instruction the operation differs as follows if halt mode was set within the interrupt service routine. <1> when a low priority interrupt request is generated only halt mode is canceled. the interrupt request is not acknowledged (pending). <2> when a high priority interrupt request (including a non-maskable interrupt request) is generated halt mode is canceled and the interrupt request is acknowledged. (b) cancellation by dcresz signal input this is the same as a normal reset operation. caution be sure to input the dcresz signal so that the setup and hold times referenced to the vbclk signal are satisfied.
chapter 6 stbc preliminary user's manual a13971ej7v0um 134 6.4 software stop mode in software stop mode, the cpu operation clock and the clock generator are stopped. the overall system is stopped, and ultra-low power consumption is achieved in which only leak current is lost. (1) setting and operation status the NB85E is switched to software stop mode by using a store instruction (st or sst instruction) or bit manipulation instruction (set1, clr1, or not1 instruction) to set the psc register. although program execution stops in software stop mode, the contents of all registers and of ram immediately before software stop mode began are maintained. the operation of all NB85E-internal peripheral i/o is also stopped. (2) cancellation of software stop mode software stop mode is canceled by a non-maskable interrupt request, an unmasked maskable interrupt request, or the input of a dcresz signal. (a) cancellation by interrupt request software stop mode is canceled by a non-maskable interrupt request not masked by the psc register or by an unmasked maskable interrupt request regardless of the priority. the following table shows the operation performed after software stop mode is canceled. caution an interrupt request that occurs while the nmi2m to nmi0m and intm bits of the power save control register (psc) are set (interrupt disabled), is invalid (software stop mode is not canceled). table 6-2. operation after software stop mode is canceled by interrupt request cancellation source interrupt enabled (ei) state interrupt disabled (di) state non-maskable interrupt request branch to handler address maskable interrupt request branch to handler address or execution of next instruction execution of next instruction the operation shown in table 6-3 is performed if software stop mode was set within the interrupt service routine.
chapter 6 stbc preliminary user's manual a13971ej7v0um 135 table 6-3. operation after setting software stop mode in interrupt service routine cancellation source interrupt service routine type when software stop mode is set priority note 1 operation low same high (id = 1) note 2 software stop mode is canceled and the interrupt request is not acknowledged (pending). maskable interrupt request high (id = 0) note 3 maskable interrupt non-maskable interrupt request _ software stop mode is canceled and the interrupt request is acknowledged. maskable interrupt request ? low same software stop mode is canceled and the interrupt request is not acknowledged (pending). non-maskable interrupt non-maskable interrupt request high software stop mode is canceled and the interrupt request is acknowledged. notes 1. the priority order of the interrupts when software stop mode is set (interrupts that were under servicing). 2. when the id bit of the psw is 1 (interrupt acknowledgement disabled) 3. when the id bit of the psw is 0 (interrupt acknowledgement enabled) (b) cancellation by dcresz signal input this is the same as a normal reset operation. caution be sure to input the dcresz signal so that the setup and hold times referenced to the vbclk signal are satisfied.
chapter 6 stbc preliminary user's manual a13971ej7v0um 136 6.5 hardware stop mode in hardware stop mode, the cpu operation clock and the clock generator are stopped. the overall system is stopped, and ultra-low power consumption is achieved in which only leak current is lost. (1) setting and operation status the NB85E is switched to hardware stop mode by inputting a low-level signal to the dcstopz pin. the NB85E is switched to hardware stop mode even if a low-level signal is input to the dcstopz pin when the NB85E is in halt mode or software stop mode. although program execution stops in hardware stop mode, the contents of all registers and of ram immediately before hardware stop mode began are maintained. the operation of all NB85E-internal peripheral i/o is also stopped. remark the NB85E may not switch to hardware stop mode correctly if the dcstopz input becomes active (low level) due to a read modify write, misalign access, etc. while the vblock signal is locked. if the dcstopz input becomes low level in the bus lock state, an internal cpu of the NB85E is stopped, but the hwstoprq signal, which controls the external clock generator, does not become active because the slave device connected to the locked bus may require clock supply. consequently, clock is not stopped and the NB85E will not switch to hardware stop mode. if the system must be switched to hardware stop mode when the dcstopz input is low level, mask the dcstopz input by the vblock signal to avoid switching to hardware stop mode while the bus is locked. (2) cancellation of hardware stop mode hardware stop mode is canceled by inputting the dcstopz or dcresz signal. (a) cancellation by dcstopz signal input hardware stop mode is canceled when the input to the dcstopz pin goes from low level to high level. the mode to which the NB85E switches after hardware stop mode is canceled differs as follows according to the status in effect before hardware stop mode was set. table 6-4. status after cancellation of hardware stop mode before hardware stop mode was set after hardware stop mode was canceled normal operation mode normal operation mode software stop mode normal operation mode halt mode halt mode (b) cancellation by dcresz signal input this is the same as a normal reset operation. caution be sure to input the dcresz signal so that the setup and hold times referenced to the vbclk signal are satisfied.
chapter 6 stbc preliminary user's manual a13971ej7v0um 137 6.6 clock control in software/hardware stop mode the NB85E and clock control circuit are connected as follows. figure 6-4. connection of NB85E and clock control circuit vbclk clock generator (cg) clk x2 x1 stprq stpak memory controller (memc) clock control circuit note swstoprq hwstoprq en NB85E cgrel note design the clock control circuit as a user logic. also, include a circuit for ensuring the oscillation stabilization time (see figures 6-5 and 6-6 ). caution in a system in which the memc is not connected to the NB85E, handle the stpak pin in either of the following ways. ? ? ? ? always input a high level. ? ? ? ? connect user logic that outputs a high level to the stpak pin to the stprq output (high level) of the NB85E. if a high level is not input to the stpak pin, the hwstoprq and swstoprq signals do not become active and shifting the stop mode becomes impossible. (1) clock control when setting or canceling software stop mode (a) when setting software stop mode (after software stop mode is set by setting the stp bit of the psc register) <1> set the stop mode request signal (stprq) to active (high level) and output it to the memory controller. <2> input the active level (high level) of the acknowledge signal (stpak) from the memory controller that received the stprq signal. <3> set the software stop mode request signal (swstoprq) to active (high level) and output it to the clock control circuit (use this swstoprq signal to stop the vbclk output from the clock control circuit). (b) when canceling software stop mode <1> input a non-maskable interrupt request (dcnmim), unmasked maskable interrupt request (intn), or the dcresz signal (m = 2 to 0, n = 63 to 0).
chapter 6 stbc preliminary user's manual a13971ej7v0um 138 <2> set the software stop mode request signal (swstoprq) to inactive (low level) and output it to the clock control circuit (clock generator starts operation). <3> after the oscillation stabilization time, input the active level (high level) of the cgrel signal from the clock control circuit simultaneous with the vbclk signal (the input of the vbclk signal returns the stprq and stpak outputs to low level). cautions 1. be sure to input the stable clock to the vbclk pin. 2. input an active level (high level) to the cgrel pin for one clock or more. when setting the software stop mode again, be sure to input an inactive level (low level) to the cgrel pin before setting.
chapter 6 stbc preliminary user's manual a13971ej7v0um 139 figure 6-5. software stop mode set/cancel timing example (a) when software stop mode is canceled by dcnmim or intn input clk vbclk (input) stprq (output) stpak (input) swstoprq (output) dcnmim (input) intn (input) cgrel (input) oscillation stabilization time 1 clock or more remarks 1. the dcnmim and intn inputs are detected at the rising edge and the interrupt request is held in the cpu. 2. m = 2 to 0, n = 63 to 0 (b) when software stop mode is canceled by dcresz input clk vbclk (input) stprq (output) stpak (input) swstoprq (output) dcresz (input) cgrel (input) oscillation stabilization time note 1 clock or more note input a high level to the dcresz pin after restarting input of vbclk.
chapter 6 stbc preliminary user's manual a13971ej7v0um 140 (2) clock control when setting or canceling hardware stop mode (a) when setting hardware stop mode <1> input the active level (low level) of the dcstopz signal. <2> set the stop mode request signal (stprq) to active (high level) and output it to the memory controller. <3> input the active level (high level) of the acknowledge signal (stpak) from the memory controller that received the stprq signal. <4> set the hardware stop mode request signal (hwstoprq) to active (high level) and output it to the clock control circuit (use this hwstoprq signal to stop the vbclk output from the clock control circuit). (b) when canceling hardware stop mode <1> input the dcresz signal or the inactive level (high level) of the dcstopz signal. <2> set the hardware stop mode request signal (hwstoprq) to inactive (low level) and output it to the clock control circuit (clock generator starts operation). <3> after the oscillation stabilization time, input the active level (high level) of the cgrel signal from the clock control circuits simultaneous with the vbclk signal (the input of the vbclk signal returns the stprq and stpak outputs to low level). cautions 1. be sure to input a stable clock to the vbclk pin. 2. input an active level (high level) to the cgrel pin for one clock or more. when setting the hardware stop mode again, be sure to input an inactive level (low level) to the cgrel pin before setting.
chapter 6 stbc preliminary user's manual a13971ej7v0um 141 figure 6-6. hardware stop mode set/cancel timing example (a) when hardware stop mode is canceled by dcstopz input clk vbclk (input) stprq (output) stpak (input) hwstoprq (output) dcstopz (input) cgrel (input) 1 clock or more oscillation stabilization time (b) when hardware stop mode is canceled by dcresz input clk vbclk (input) stprq (output) stpak (input) hwstoprq (output) dcstopz (input) cgrel (input) dcresz (input) note 1 note 2 1 clock or more oscillation stabilization time notes 1. input a high level to the dcresz pin after restarting input of vbclk. 2. input a high level to the dcstopz pin before inputting a high level to the dcresz pin.
preliminary user?s manual a13971ej7v0um 142 chapter 7 dmac the dma control unit (dmac) controls data transfers between memory and peripheral macros or between memory and memory based on dma transfer requests issued according to the dmarq3 to dmarq0 pins or software triggers (memory means ram or external memory). 7.1 features ? four independent dma channels ? transfer units: 8 bits, 16 bits, or 32 bits ? maximum transfer count: 65536 (2 16 ) ? two transfer types flyby (one-cycle) transfer two-cycle transfer ? four transfer modes single transfer mode single-step transfer mode line transfer mode (four bus cycle transfer mode) (in two-cycle transfer, the operation from read to write is repeated four times) block transfer mode ? transfer requests requests by dmarq3 to dmarq0 pin input requests by software ? transfer objects between ram and peripheral macros between ram and external memory between ram and ram between external memory and peripheral macros between external memory and external memory (transfer between little endian area and big endian area is possible) ? terminal count output signals (dmtco3 to dmtco0) ? next address setting function
chapter 7 dmac preliminary user?s manual a13971ej7v0um 143 7.2 configuration dma destination address register (ddanh / ddanl) dma channel control register (dchcn ) dma source address register (dsanh/ dsanl) dma transfer count register (dbcn ) dma addressing control register (dadcn ) count control channel control address control data control ram memory controller NB85E dmac bcu bbr dmtcon idmastp dmarqn dmactvn vsb npb vdb external memory peripheral macro peripheral macro remark n = 3 to 0
chapter 7 dmac preliminary user?s manual a13971ej7v0um 144 7.3 transfer objects (1) transfer types table 7-1 shows the relationships between transfer types and transfer objects. caution operation is not guaranteed when a transfer is performed using a combination of transfer source and transfer destination marked by an ?no? in table 7-1. table 7-1. relationships between transfer type and transfer object transfer destination two-cycle transfer flyby transfer vsb npb ram vsb npb ram vsb yes yes yes yes note no no npb yes yes yes no no no transfer source ram yes yes yes no no no note the transfer can be performed only when using the memc (NB85E500/nu85e500) associated with the flyby transfer. remark yes: transfer enabled no: transfer disabled vsb: external memory or peripheral macro on the vsb npb: peripheral macro on the npb (2) wait function table 7-2 shows the relationships between the wait function and transfer objects. table 7-2. relationships between wait function and transfer object transfer object wait function vsb set by memc (NB85E500/nu85e500, nu85e502) npb set by vswc register ram no wait 7.4 dma channel priorities dma channel prioritization is fixed as follows. dma channel 0 > dma channel 1 > dma channel 2 > dma channel 3 this prioritization is only valid in the ti state. during a block transfer, the channel used for transfer is never switched. during a single-step transfer, if a higher priority dma transfer request is generated during the period when the bus is released (ti), the higher priority dma transfer is performed.
chapter 7 dmac preliminary user?s manual a13971ej7v0um 145 7.5 control registers 7.5.1 dma source address registers 0 to 3 (dsa0 to dsa3) these registers are used to set the dma transfer source addresses (28 bits each) for dma channels n (n = 0 to 3). they are divided into two 16-bit registers, dsanh and dsanl, respectively. since they are two-stage fifo-configuration buffer registers, the transfer source address of a new dma transfer can be set during a dma transfer (see 7.6 next address setting function ). when a flyby transfer is set according to the ttyp bit of the dma addressing control registers n (dadcn), the external memory addresses are set by the dsan registers. at this time, any settings of the dma destination address registers n (ddan) are ignored. (1) dma source address registers 0h to 3h (dsa0h to dsa3h) these registers can be read or written in 16-bit units. figure 7-1. dma source address registers 0h to 3h (dsa0h to dsa3h) 1514131211109876543210 dsa0hir000 sa 27 sa 26 sa 25 sa 24 sa 23 sa 22 sa 21 sa 20 sa 19 sa 18 sa 17 sa 16 address fffff082h after reset undefined dsa1hir000 sa 27 sa 26 sa 25 sa 24 sa 23 sa 22 sa 21 sa 20 sa 19 sa 18 sa 17 sa 16 address fffff08ah after reset undefined dsa2hir000 sa 27 sa 26 sa 25 sa 24 sa 23 sa 22 sa 21 sa 20 sa 19 sa 18 sa 17 sa 16 address fffff092h after reset undefined dsa3hir000 sa 27 sa 26 sa 25 sa 24 sa 23 sa 22 sa 21 sa 20 sa 19 sa 18 sa 17 sa 16 address fffff09ah after reset undefined bit position bit name function 15 ir specifies the dma transfer source. 0: external memory or peripheral macro 1: ram 11 to 0 sa27 to sa16 sets the dma transfer source address (a27 to a16). during a dma transfer, the next dma transfer source address is maintained. for a flyby transfer, the external memory address is maintained.
chapter 7 dmac preliminary user?s manual a13971ej7v0um 146 (2) dma source address registers 0l to 3l (dsa0l to dsa3l) these registers can be read or written in 16-bit units. figure 7-2. dma source address registers 0l to 3l (dsa0l to dsa3l) 1514131211109876543210 dsa0l sa 15 sa 14 sa 13 sa 12 sa 11 sa 10 sa 9 sa 8 sa 7 sa 6 sa 5 sa 4 sa 3 sa 2 sa 1 sa 0 address fffff080h after reset undefined dsa1l sa 15 sa 14 sa 13 sa 12 sa 11 sa 10 sa 9 sa 8 sa 7 sa 6 sa 5 sa 4 sa 3 sa 2 sa 1 sa 0 address fffff088h after reset undefined dsa2l sa 15 sa 14 sa 13 sa 12 sa 11 sa 10 sa 9 sa 8 sa 7 sa 6 sa 5 sa 4 sa 3 sa 2 sa 1 sa 0 address fffff090h after reset undefined dsa3l sa 15 sa 14 sa 13 sa 12 sa 11 sa 10 sa 9 sa 8 sa 7 sa 6 sa 5 sa 4 sa 3 sa 2 sa 1 sa 0 address fffff098h after reset undefined bit position bit name function 15 to 0 sa15 to sa0 sets the dma transfer source address (a15 to a0). during a dma transfer, the next dma transfer source address is maintained. for a flyby transfer, the external memory address is maintained.
chapter 7 dmac preliminary user?s manual a13971ej7v0um 147 7.5.2 dma destination address registers 0 to 3 (dda0 to dda3) these registers are used to set the dma transfer destination addresses (28 bits each) for dma channels n (n = 0 to 3). they are divided into two 16-bit registers, ddanh and ddanl, respectively. since they are two-stage fifo-configuration buffer registers, the transfer destination address of a new dma transfer can be set during a dma transfer (see 7.6 next address setting function ). when a flyby transfer is set according to the ttyp bit of the dma addressing control registers n (dadcn), any setting of these registers are ignored. (1) dma destination address registers 0h to 3h (dda0h to dda3h) these registers can be read or written in 16-bit units. figure 7-3. dma destination address registers 0h to 3h (dda0h to dda3h) 1514131211109876543210 dda0h ir 0 0 0 da 27 da 26 da 25 da 24 da 23 da 22 da 21 da 20 da 19 da 18 da 17 da 16 address fffff086h after reset undefined dda1h ir 0 0 0 da 27 da 26 da 25 da 24 da 23 da 22 da 21 da 20 da 19 da 18 da 17 da 16 address fffff08eh after reset undefined dda2h ir 0 0 0 da 27 da 26 da 25 da 24 da 23 da 22 da 21 da 20 da 19 da 18 da 17 da 16 address fffff096h after reset undefined dda3h ir 0 0 0 da 27 da 26 da 25 da 24 da 23 da 22 da 21 da 20 da 19 da 18 da 17 da 16 address fffff09eh after reset undefined bit position bit name function 15 ir specifies the dma transfer destination. 0: external memory or peripheral macro 1: ram 11 to 0 da27 to da16 sets the dma transfer destination address (a27 to a16). during a dma transfer, the next dma transfer destination address is maintained. for a flyby transfer, this is ignored.
chapter 7 dmac preliminary user?s manual a13971ej7v0um 148 (2) dma destination address registers 0l to 3l (dda0l to dda3l) these registers can be read or written in 16-bit units. figure 7-4. dma destination address registers 0l to 3l (dda0l to dda3l) 1514131211109876543210 dda0l da 15 da 14 da 13 da 12 da 11 da 10 da 9 da 8 da 7 da 6 da 5 da 4 da 3 da 2 da 1 da 0 address fffff084h after reset undefined dda1l da 15 da 14 da 13 da 12 da 11 da 10 da 9 da 8 da 7 da 6 da 5 da 4 da 3 da 2 da 1 da 0 address fffff08ch after reset undefined dda2l da 15 da 14 da 13 da 12 da 11 da 10 da 9 da 8 da 7 da 6 da 5 da 4 da 3 da 2 da 1 da 0 address fffff094h after reset undefined dda3l da 15 da 14 da 13 da 12 da 11 da 10 da 9 da 8 da 7 da 6 da 5 da 4 da 3 da 2 da 1 da 0 address fffff09ch after reset undefined bit position bit name function 15 to 0 da15 to da0 sets the dma transfer destination address (a15 to a0). during a dma transfer, the next dma transfer destination address is maintained. for a flyby transfer, this is ignored.
chapter 7 dmac preliminary user?s manual a13971ej7v0um 149 7.5.3 dma transfer count registers 0 to 3 (dbc0 to dbc3) these 16-bit registers are used to set the transfer counts for dma channels n (n = 0 to 3). these registers maintain the remaining transfer count during a dma transfer. since they are two-stage fifo-configuration buffer registers, the transfer count of a new dma transfer can be set during a dma transfer (see 7.6 next address setting function ). these registers are decremented by 1 for each transfer that is performed. transfer ends when a borrow occurs. these registers can be read or written in 16-bit units. note that in the case of line transfers, when the dbcn register is 0003h (4 transfers) this becomes one line transfer. for a setting in which the transfer count cannot be divided by 4, the sections that can be line transferred are (line) transferred first, then the remaining indivisible section is transferred as single transfers. figure 7-5. dma transfer count registers 0 to 3 (dbc0 to dbc3) 1514131211109876543210 dbc0 bc 15 bc 14 bc 13 bc 12 bc 11 bc 10 bc 9 bc 8 bc 7 bc 6 bc 5 bc 4 bc 3 bc 2 bc 1 bc 0 address fffff0c0h after reset undefined dbc1 bc 15 bc 14 bc 13 bc 12 bc 11 bc 10 bc 9 bc 8 bc 7 bc 6 bc 5 bc 4 bc 3 bc 2 bc 1 bc 0 address fffff0c2h after reset undefined dbc2 bc 15 bc 14 bc 13 bc 12 bc 11 bc 10 bc 9 bc 8 bc 7 bc 6 bc 5 bc 4 bc 3 bc 2 bc 1 bc 0 address fffff0c4h after reset undefined dbc3 bc 15 bc 14 bc 13 bc 12 bc 11 bc 10 bc 9 bc 8 bc 7 bc 6 bc 5 bc 4 bc 3 bc 2 bc 1 bc 0 address fffff0c6h after reset undefined bit position bit name function 15 to 0 bc15 to bc0 sets the transfer count. during a dma transfer, the remaining transfer count is maintained. dbcn status 0000h transfer 1 or remaining transfer count 0001h transfer 2 or remaining transfer count ? ? ffffh transfer 65536 (2 16 ) or remaining transfer count remark n = 0 to 3
chapter 7 dmac preliminary user?s manual a13971ej7v0um 150 7.5.4 dma addressing control registers 0 to 3 (dadc0 to dadc3) these 16-bit registers are used to control the dma transfer operation mode for dma channels n (n = 0 to 3). these registers can be read or written in 16-bit units. caution these registers cannot be accessed during a dma transfer. figure 7-6. dma addressing control registers 0 to 3 (dadc0 to dadc3) (1/2) 1514131211109876543210 dadc0 ds 1 ds 0 000000 sad 1 sad 0 dad 1 dad 0 tm1 tm0 ttyp tdir address fffff0d0h after reset 0000h dadc1 ds 1 ds 0 000000 sad 1 sad 0 dad 1 dad 0 tm1 tm0 ttyp tdir address fffff0d2h after reset 0000h dadc2 ds 1 ds 0 000000 sad 1 sad 0 dad 1 dad 0 tm1 tm0 ttyp tdir address fffff0d4h after reset 0000h dadc3 ds 1 ds 0 000000 sad 1 sad 0 dad 1 dad 0 tm1 tm0 ttyp tdir address fffff0d6h after reset 0000h bit position bit name function 15, 14 ds1, ds0 sets the transfer data size for a dma transfer. ds1 ds0 transfer data size 0 0 8 bits 0 1 16 bits 1 0 32 bits 1 1 setting prohibited 7, 6 sad1, sad0 sets the count direction of the transfer source addresses for dma channels n (n = 0 to 3). sad1 sad0 count direction 0 0 increment 0 1 decrement 10fixed 1 1 setting prohibited
chapter 7 dmac preliminary user?s manual a13971ej7v0um 151 figure 7-6. dma addressing control registers 0 to 3 (dadc0 to dadc3) (2/2) bit position bit name function 5, 4 dad1, dad0 sets the count direction of the transfer destination addresses for dma channels n (n = 0 to 3). dad1 dad0 count direction 0 0 increment 0 1 decrement 10fixed 1 1 setting prohibited 3, 2 tm1, tm0 sets the transfer mode used for dma transfers. tm1 tm0 transfer mode 0 0 single transfer mode 0 1 single-step transfer mode 1 0 line transfer mode 1 1 block transfer mode 1 ttyp sets the dma transfer type. 0: two-cycle transfer 1: flyby transfer note 0 tdir sets the transfer direction used for transfers between peripheral macros and external memory. the setting is valid only for flyby transfers and is ignored for two-cycle transfers. 0: external memory to peripheral macro (read) 1: peripheral macro to external memory (write) remark n = 0 to 3 note valid only when using the memc associated with the flyby transfer.
chapter 7 dmac preliminary user?s manual a13971ej7v0um 152 7.5.5 dma channel control registers 0 to 3 (dchc0 to dchc3) these 8-bit registers are used to control the dma transfer operation mode for dma channels n (n = 0 to 3). these registers can be read or written in 8-bit or 1-bit units (however, bit 7 can only be read and bits 2 and 1 can only be written. if bits 2 and 1 are read, the value 0 is read). figure 7-7. dma channel control registers 0 to 3 (dchc0 to dchc3) 76543210 dchc0 tc0 0 0 0 mle0 init0 stg0 en0 address fffff0e0h after reset 00h dchc1 tc1 0 0 0 mle1 init1 stg1 en1 address fffff0e2h after reset 00h dchc2 tc2 0 0 0 mle2 init2 stg2 en2 address fffff0e4h after reset 00h dchc3 tc3 0 0 0 mle3 init3 stg3 en3 address fffff0e6h after reset 00h bit position bit name function 7 tcn this is a status bit that indicates whether or not dma transfer has ended for dma channel n. this bit can only be read. this bit is set (1) when dma transfer ends. it is cleared (0) when it is read. 0: dma transfer has not ended 1: dma transfer has ended 3 mlen if this bit is set (1) when a terminal count is output, the enn bit is not cleared (0), and the status in which dma transfer is permitted continues. also, the next dma transfer request is acknowledged even if the tcn bit is not read. if this bit is cleared (0) when a terminal count is output, the enn bit is cleared (0), and the status in which dma transfer is prohibited occurs. when the next dma transfer request is made, if the tcn bit is read, the enn bit must be set (1). 2 initn if this bit is set (1), the dma transfer is forcibly terminated. 1 stgn if this bit is set (1) during the status in which dma transfer is permitted (tcn bit = 0, enn bit = 1), the dma transfer begins. 0 enn sets whether dma transfer is permitted or prohibited for dma channel n. this bit is cleared (0) when the dma transfer is completed. it is also cleared (0) when an idmastp signal is input or when transfer is forcibly terminated by setting (1) the initn bit. 0: dma transfer is prohibited 1: dma transfer is permitted remark n = 0 to 3
chapter 7 dmac preliminary user?s manual a13971ej7v0um 153 7.5.6 dma disable status register (ddis) this register maintains the contents of the enn bit of the dchcn register when an idmastp signal is input (n = 0 to 3). this register is read-only in 8-bit or 1-bit units. figure 7-8. dma disable status register (ddis) 76543210 ddis0000ch3ch2ch1ch0 address fffff0f0h after reset 00h bit position bit name function 3 to 0 ch3 to ch0 reflects the contents of the enn bit of the dchcn register when an idmastp signal is input. the contents of this register are maintained until the next idmastp signal is input or a system reset occurs. 7.5.7 dma restart register (drst) this register is used to restart a dma transfer that was forcibly interrupted by inputting an idmastp signal. the enn bits of this register are linked respectively with the enn bits of the dchcn registers (n = 0 to 3). after a dma transfer was forcibly interrupted by inputting the idmastp signal, the dma channel for which the transfer was interrupted is confirmed from the contents of the ddis register, and the dma transfer can be restarted by setting (1) the enn bit of the corresponding dma channel. this register can be read or written in 8-bit or 1-bit units. figure 7-9. dma restart register (drst) 76543210 drst0000en3en2en1en0 address fffff0f2h after reset 00h bit position bit name function 3 to 0 en3 to en0 sets whether dma transfer is permitted or prohibited for dma channel n. this bit is cleared (0) when the dma transfer ends due to the output of a terminal count. it is also cleared (0) when an idmastp signal is input or when dma transfer is forcibly terminated by setting (1) the initn bit of the dchcn register. 0: dma transfer is prohibited 1: dma transfer is permitted
chapter 7 dmac preliminary user?s manual a13971ej7v0um 154 7.6 next address setting function the dma source address registers (dsanh and dsanl), dma destination address registers (ddanh and ddanl), and dma transfer count registers (dbcn) are two-stage fifo-configuration buffer registers (n = 0 to 3). when a terminal count signal (dmtcon) is output, these registers are automatically rewritten with the values that had just been set before the signal is output. therefore, if a new dma transfer is set for these registers during a dma transfer, the transfer can begin only when the enn bit of the dchcn register is set (1). figure 7-10 shows the buffer register configuration. figure 7-10. buffer register configuration master register reading of data slave register address/ count controller n p b writing of data
chapter 7 dmac preliminary user?s manual a13971ej7v0um 155 7.7 dma bus state 7.7.1 bus state types dmac bus cycles consist of the 13 states shown below. (1) ti state this is an idle state in which there is no access request. the dmarq3 to dmarq0 signals are sampled at the rising edge of the vbclk signal. (2) t0 state this is a dma transfer ready state (there is a dma transfer request, and the bus access right has been acquired for the first dma transfer). (3) t1r state this is the state to which the dmac moves first for a two-cycle transfer read. address driving begins. after the t1r state, the dmac always transitions to the t2r state. (4) t1ri state this is a state in which the dmac is awaiting an acknowledge signal for an external memory read request. after the last t1ri state, the dmac always transitions to the t2r state. (5) t2r state this is a wait state or the last state of a two-cycle transfer read. in the last t2r state, read data is sampled. after the read data is sampled, the dmac always transitions to the t1w state. (6) t2ri state this is a dma transfer ready state for a dma transfer to ram (the bus access right has been acquired for a dma transfer to ram). after the last t2ri state, the dmac always transitions to the t1w state. (7) t1w state this is the state to which the dmac moves first for a two-cycle transfer write. address driving begins. after the t1w state, the dmac always transitions to the t2w state. (8) t1wi state this is a state in which the dmac is awaiting an acknowledge signal for an external memory write request. after the last t1wi state, the dmac always transitions to the t2w state. (9) t2w state this is a wait state or the last state of a two-cycle transfer write. in the last t2w state, the write strobe signal is made inactive. (10) t1fh state this is the basic state of a flyby transfer and is the execution cycle of that transfer. after the t1fh state, the dmac transitions to the t2fh state.
chapter 7 dmac preliminary user?s manual a13971ej7v0um 156 (11) t1fhi state this is the last state of a flyby transfer, and the dmac is awaiting the end of the transfer. after the t1fhi state, the bus is released, and the dmac transitions to the te state. (12) t2fh state this is the state in which the dmac judges whether or not to continue flyby transfers. if the next transfer is executed in block transfer mode, the dmac moves to the t1fh state after the t2fh state. in other modes, if a wait has occurred, the dmac transitions to the t1fhi state. if no wait has occurred, the bus is released, and the dmac transitions to the te state. (13) te state this is the state in which the dma transfer is completed. the dmac generates a terminal count signal (dmtcon) and initializes other types of internal signals (n = 3 to 0). after the te state, the dmac always transitions to the ti state.
chapter 7 dmac preliminary user?s manual a13971ej7v0um 157 7.7.2 dmac bus cycle state transitions figure 7-11. dmac bus cycle state transition diagram (a) two-cycle transfer t1w t2ri t1r t0 ti t1ri t2r t1wi t2w te ti (b) flyby transfer ti ti t0 t1fh t2fh t1fhi te
chapter 7 dmac preliminary user?s manual a13971ej7v0um 158 7.8 transfer modes 7.8.1 single transfer mode in single transfer mode, the dmac releases the bus after each byte, halfword, or word transfer. if there is a subsequent dma transfer request, a single transfer is performed again. this operation continues until a terminal count occurs. if a higher priority dma transfer request is generated while the dmac has released the bus, the higher priority dma transfer request always takes precedence. however, if a lower priority dma transfer request is generated within one clock after the end of a single transfer, even if the previous higher priority dma transfer request signal stays active, this request is not prioritized, and the next dma transfer after the bus is released for the cpu is a transfer based on the newly generated, lower priority dma transfer request. figures 7-12 to 7-15 show examples for single transfer. figure 7-12. single transfer example 1 cpu dma3 cpu cpu dma3 cpu cpu cpu cpu cpu dma3 cpu dma3 dma3 cpu cpu cpu dmarq3 (input) cpu cpu dma channel 3 terminal count note note note note note the bus is always released. figure 7-13 shows a single transfer mode example in which a higher priority dma transfer request is generated. dma channels 0 to 2 are used for a block transfer, and channel 3 is used for a single transfer. figure 7-13. single transfer example 2 dma1 dma2 cpu dma2 cpu dma3 cpu cpu cpu dma3 cpu dma0 dma0 cpu dma1 dmarq3 (input) cpu dma3 dmarq2 (input) dmarq1 (input) dmarq0 (input) note note note note dma channel 0 terminal count dma channel 2 terminal count dma channel 3 terminal count dma channel 1 terminal count note the bus is always released.
chapter 7 dmac preliminary user?s manual a13971ej7v0um 159 figure 7-14 shows a single transfer mode example in which a lower priority dma transfer request is generated within one clock after the end of a single transfer. dma channels 0, 3 are used for a single transfer. when two dma transfer request signals are activated at the same time, the two dma transfers are performed alternately. figure 7-14. single transfer example 3 note the bus is always released. figure 7-15 shows a single transfer mode example in which two or more lower priority dma transfer requests are generated within one clock after the end of a single transfer. dma channels 0, 2, and 3 are used for a single transfer. when three or more dma transfer request signals are activated at the same time, always the two highest priority dma transfers are performed alternately. figure 7-15. single transfer example 4 note the bus is always released. cpu cpu dma3 dma0 cpu dma0 cpu cpu cpu cpu dma0 cpu dma0 dma3 cpu cpu dma0 dmarq3 (input) cpu dma0 dma channel 0 terminal count note note note note dmarq0 (input) dma channel 3 terminal count note note note dma2 cpu dma3 cpu cpu dma3 cpu cpu dma2 dma0 cpu dmarq3 (input) dma0 note note note dmarq2 (input) note note dmarq0 (input) dma2 cpu dma channel 0 terminal count note dma3 cpu dma2 cpu cpu dma3 dma channel 3 terminal count note cpu cpu note dma channel 2 terminal count note
chapter 7 dmac preliminary user?s manual a13971ej7v0um 160 7.8.2 single-step transfer mode in single-step transfer mode, the dmac releases the bus after each byte, halfword, or word transfer. once a dma transfer request signal (dmarq3 to dmarq0) is received, this operation continues until a terminal count occurs. if a higher priority dma transfer request is generated while the dmac has released the bus, the higher priority dma transfer request always takes precedence. figures 7-16 and 7-17 show single-step transfer mode examples. figure 7-16. single-step transfer example 1 dma1 cpu cpu cpu cpu cpu cpu cpu cpu dma1 cpu cpu dma1 dma1 cpu dmarq1 (input) cpu cpu dma channel 1 terminal count note note note note the bus is always released. figure 7-17. single-step transfer example 2 dma0 dma0 cpu cpu dma1 cpu cpu cpu cpu dma1 cpu cpu dma1 dma0 cpu dmarq1 (input) dma1 cpu dmarq0 (input) dma channel 0 terminal count dma channel 1 terminal count note note note note note note note the bus is always released.
chapter 7 dmac preliminary user?s manual a13971ej7v0um 161 7.8.3 line transfer mode in line transfer mode, the dmac releases the bus after every four byte, halfword, or word transfers. if there is a subsequent dma transfer request, four transfers are performed again. this operation continues until a terminal count occurs. in two-cycle transfer, the operation from read to write is repeated four times. if a higher priority dma transfer request is generated while the dmac has released the bus, the higher priority dma transfer request always takes precedence. however, if a lower priority dma transfer request is generated within one clock after the end of a line transfer, even if the previous higher priority dma transfer request signal stays active, this request is not prioritized, and the next dma transfer after the bus is released for the cpu is a transfer based on the newly generated, lower priority dma transfer request. figures 7-18 to 7-21 show examples for line transfer. figure 7-18. line transfer example 1 dmarq3 (input) dma3 dma3 cpu dma3 dma3 dma3 cpu cpu dma3 cpu dma3 dma3 dma3 dma3 cpu dma3 dma3 cpu cpu dma channel 3 terminal count note note note the bus is always released. figure 7-19 shows a line transfer mode example in which a higher priority dma transfer request is generated. dma channels 0 to 2 are used for a block transfer, and channel 3 is used for a line transfer. figure 7-19. line transfer example 2 dma1 dma2 cpu dma2 cpu dma3 dma3 cpu dma0 dma0 cpu dma1 cpu cpu cpu cpu dmarq3 (input) dmarq2 (input) dmarq1 (input) dmarq0 (input) note note note note dma3 dma3 dma channel 0 terminal count dma channel 2 terminal count dma channel 1 terminal count dma3 dma3 dma3 dma3 note dma channel 3 terminal count note the bus is always released.
chapter 7 dmac preliminary user?s manual a13971ej7v0um 162 figures 7-20 and 7-21 show line transfer mode examples in which a lower priority dma transfer request is generated within one clock after the end of a line transfer. when two dma transfer request signals are activated at the same time, the two dma transfers are performed alternately. dma channels 0 and 3 in figure 7-20 are used for line transfer. figure 7-20. line transfer example 3 note the bus is always released. dma channel 0 in figure 7-21 is used for a single transfer, and channel 3 is used for a line transfer. figure 7-21. line transfer example 4 note the bus is always released. dma3 cpu dma0 cpu dma0 dma0 dma0 dma3 cpu dma3 dma3 dmarq3 (input) dma0 note note dmarq0 (input) dma0 dma0 dma channel 0 terminal count cpu dma3 dma3 dma3 cpu dma3 dma channel 3 terminal count note cpu dma0 dma3 cpu cpu cpu dma0 cpu dma0 dma3 cpu dma3 dma3 dmarq3 (input) dma0 note note dmarq0 (input) dma3 dma3 dma channel 3 terminal count dma3 dma3 cpu dma0 cpu cpu dma channel 0 terminal count cpu note note note
chapter 7 dmac preliminary user?s manual a13971ej7v0um 163 7.8.4 block transfer mode in block transfer mode, once transfer begins, the transfers continue without releasing the bus until a terminal count occurs. no other dma transfer requests are acknowledged during a block transfer. after the block transfer ends and the dmac has released the bus, another dma transfer can be acknowledged. although it is prohibited to insert a cpu bus cycle during a block transfer, bus mastership can be transferred even during a block transfer in response to a request by the external bus master (including sdram refresh). figure 7-22 shows a block transfer mode example. it is a block transfer mode example in which a higher priority dma transfer request is generated. dma channels 2 and 3 are used for a block transfer. figure 7-22. block transfer example dma3 cpu dma3 dma2 dma2 dma2 cpu cpu cpu dma3 dma3 dma3 dma3 dma3 dma3 dmarq3 (input) dma2 dma2 dma channel 3 terminal count dmarq2 (input) the bus is always released
chapter 7 dmac preliminary user?s manual a13971ej7v0um 164 7.8.5 one-time transfer when executing single transfers using dmarqn signal when executing single transfers to the external memory using the dmarqn signal input, in order to perform the transfer only once, it is necessary to make the dmarqn signal inactive within 2 clocks of the end of the write cycle of a 2-cycle single transfer (exceeding 2 clocks makes the transfer continuous) (n = 3 to 0). figure 7-23. one-time transfer when executing single transfers using dmarqn signal vbttyp1, vbttyp0 (output) vba27 to vba0 (output) vbwrite (output) vbstz (output) vbwait (input) vbd31 to vbd0 (i/o) vbclk (input) vbdc (output) dmarqn (input) dmactvn (output) 0h 2h 3h 2h 0h 2h 0h 3h read cycle write cycle 2-cycle single transfer the dmarqn signal must be inactive by this point remarks 1. the levels of broken-line portions indicate the undefined state (weak unknown) entered when the NB85E internal bus holder is driving. 2. the o marks indicate the sampling timing. 3. n = 3 to 0
chapter 7 dmac preliminary user?s manual a13971ej7v0um 165 7.9 transfer types 7.9.1 two-cycle transfer in a 2-cycle transfer, data is transferred in 2 cycles: a read cycle (transfer source to dmac) and a write cycle (dmac to transfer destination). in the first cycle, the transfer source address is output to read data from the transfer source to the dmac. in the second cycle, the transfer destination address is output to write data from the dmac to the transfer destination. caution a one-clock idle period is always inserted between a read cycle and a write cycle. 7.9.2 flyby transfer a flyby transfer can be executed only when the memc supports flyby transfers. since a flyby transfer transfers data in a single cycle, a memory address is always output regardless of whether it is the transfer source or transfer destination, and the memory or wrz/iordz or rdz/iowrz singal of the external i/o is made active at the same time. the external i/o is selected according to the dmactv3 to dmactv0 signals. caution flyby transfer between sdram that use an sdram controller (nu85e502) is disabled. 7.10 dma transfer start factors dma transfer can be started by the following two factors. (1) request by external pin (dmarqn) if the enn bit of the dchcn register is set to 1 and the tcn bit is set to 0, the dmarqn signal becomes active in ti state. if the dmarqn signal becomes active in ti state, the dmac moves to t0 state and dma transfer begins. (2) request by software if the stgn, enn, and tcn bits of the dchcn register are set as follows, dma transfer begins (n = 0 to 3). ? stgn bit = 1 ? enn bit = 1 ? tcn bit = 0
chapter 7 dmac preliminary user?s manual a13971ej7v0um 166 7.11 output when dma transfer is complete the terminal count signal (dmtcon) becomes active for only one clock in the final dma transfer cycle (n = 3 to 0). for details of the timing that outputs the dmtcon signal, refer to figure 7-27. figure 7-24. timing example of terminal count signals (dmtco3 to dmtco0) cpu cpu cpu dman dman dman dma channel n terminal count cpu dmarqn (input) dmtcon (output) remark n = 3 to 0
chapter 7 dmac preliminary user?s manual a13971ej7v0um 167 7.12 forcible interruption dma transfer can be forcibly interrupted by inputting the idmastp signal during the dma transfer. at this time, the dmac clears (0) the enn bit of the dchcn register of all channels to set the state in which dma transfer is prohibited, completes the dma transfer that was being executed when the idmastp signal was input, and the bus releases to the cpu (n = 0 to 3). for single-step transfer mode, block transfer mode, or line transfer mode, the dma transfer request is maintained in the dmac. when the enn bit is set (1), the dma transfer is restarted from the point at which the dma transfer was interrupted. for single transfer mode, when the enn bit is set (1), the next dma transfer request is acknowledged and dma transfer begins. caution to forcibly interrupt dma transfer and stop the next transfer from occurring, the idmastp signal must be made active before the end of the dma transfer currently under execution. moreover, although it is possible to restart dma transfer following an interruption, this transfer cannot be executed under new settings (new conditions). execute dma transfer under new settings either after the end of the current transfer or after transfer has been forcibly terminated by setting the initn bit of the dchcn register (n = 0 to 3). figure 7-25. dma transfer forcible interruption example dma transfer dma transfer suspended dma transfer dma transfer suspended 01h ddis register 01h drst register en0 bit of dchc register transfer restart forcible interruption forcible interruption idmastp (input)
chapter 7 dmac preliminary user?s manual a13971ej7v0um 168 7.13 forcible termination by setting (1) the initn bit of the dchcn register during a dma transfer, it is possible to forcibly terminate the dma transfer under execution. the following is an example of the operation of a forcible termination (n = 0 to 3). caution the setting (1) of the initn bit is performed when the vsb has been released to the cpu (n = 0 to 3). therefore, because the vsb is locked until the dma transfer has completely finished in a block transfer using the vsb, it is not possible to exercise a forcible termination during this transfer. figure 7-26. dma transfer forcible termination example (1/2) (a) block transfer using dma channel 3 begins during block transfer using dma channel 2 cpu dma3 dma3 dma3 dma3 cpu cpu cpu cpu cpu dma2 dma2 dma2 dma2 dma2 dmarq3 (input) cpu cpu dmarq2 (input) en3 bit = 1 tc3 bit = 0 en3 bit 0 tc3 bit 1 dsa3, dda3, dbc3, dadc3, dchc3 set register en2 bit = 1 tc2 bit = 0 dsa2, dda2, dbc2, dadc2, dchc2 set register dchc2 (init2 bit = 1) set register en2 bit 0 tc2 bit = 0 dma channel 3 terminal count dma channel 3 transfer begins dma channel 2 transfer is forcibly terminated and the bus is released
chapter 7 dmac preliminary user?s manual a13971ej7v0um 169 figure 7-26. dma transfer forcible termination example (2/2) (b) the transfer is forcibly terminated during block transfer using dma channel 1 and a transfer with another condition is executed dma1 cpu cpu cpu cpu dma1 cpu cpu cpu cpu dma1 dma1 dma1 dma1 dma1 dmarq1 (input) dma1 dma1 dma channel 1 terminal count dma channel 1 transfer is forcibly terminated and the bus is released en1 bit = 1 tc1 bit = 0 en1 bit 0 tc1 bit 1 dsa1, dda1, dbc1, dadc1, dchc1 set register cpu dsa1, dda1, dbc1 set register dchc1 (init1 bit = 1) set register dadc1, dchc1 set register en1 bit 0 tc1 bit = 0 en1 bit 1 tc1 bit = 0 remark since the dsan, ddan, and dbcn registers are buffer registers, the next transfer condition can be set even during a dma transfer. however, a setting in the dadcn register is ignored (see 7.6 next address setting function ).
chapter 7 dmac preliminary user?s manual a13971ej7v0um 170 7.14 dma transfer timing examples examples of the dma transfer timing in each transfer mode are shown in the following pages. the NB85E500, the nu85e500, and the nu85e502 are provided as memcs for the NB85E. this section gives examples in the case that the NB85E500 and the nu85e502 are used. (1) two-cycle transfer figures 7-27 to 7-30 show examples of the timing of two-cycle transfers between external srams connected to the memc (NB85E500). figures 7-31 and 7-32 show examples of the timing of two-cycle transfers between ram connected to the vdb and sdram connected to the memc (nu85e502). remarks 1. the levels of the broken-line portions of the vbttyp1, vbttyp0, vba27 to vba0, vbd31 to vbd0, vbctyp2 to vbctyp0, vbseq2 to vbseq0, vbsize1, vbsize0, vbwait, vbahld, and vblast signals indicate the undefined state (weak unknown) entered when the NB85E internal bus holder is driving. the levels of the broken-line portions of the a25 to a0 and d31 to d0 signals are undefined (except those portions indicating hi-z). 2. the o marks indicate the sampling timing. 3. n = 3 to 0 figure 7-27 shows an example of the timing of a two-cycle single transfer (between external srams connected to the NB85E500). the settings of the registers in this figure are as follows. [register settings] ? dbcn register = 0001h (2 transfers) ? asc register note = 0000h (no address setting wait states) ? bcc register note = 0000h (no idle states) ? dwc0 register note = 7377h (cs2 wait states = 3) note an NB85E500 register.
chapter 7 dmac preliminary user?s manual a13971ej7v0um 171 figure 7-27. example of two-cycle single transfer timing (between external srams connected to NB85E500) note these are NB85E500 signals. vbttyp1,vbttyp0 (output) vba27 to vba0 (output) vbwrite (output) vbstz (output) vbwait (input) vbahld (input) vblast (input) vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbsize1,vbsize0 (output) vdcsz7 to vdcsz0 (output) d31 to d0 (i/o) note rdz (output) note a25 to a0 (output) note vbseq2 to vbseq0 (output) vbclk (input) vbdc (output) dmarqn (input) dmactvn (output) dmtcon (output) wrz3 to wrz0 (output) note csz7 to csz0 (output) note vblock (output) 0h 2h 3h 0h 2h 0h 3h 2h 3h 0h 2h 3h 0h fh 0h fh 0h fh 0h fh 0h fh 6h 6h 6h 6h 0h 0h 0h 0h 2h 2h 2h 2h ffh fbh ffh fbh ffh fbh ffh fbh ffh l l hi-z hi-z hi-z hi-z fh 0h 0h fh fh ffh fbh ffh fbh ffh fbh ffh fbh ffh read cycle write cycle 2-cycle single transfer cpu cycle read cycle write cycle 2-cycle single transfer hi-z
chapter 7 dmac preliminary user?s manual a13971ej7v0um 172 figure 7-28 shows an example of the timing of a two-cycle single-step transfer (between external srams connected to the NB85E500). the settings of the registers in this figure are as follows. [register settings] ? dbcn register = 0002h (3 transfers) ? asc register note = 0000h (no address setting wait states) ? bcc register note = 0000h (no idle states) ? dwc0 register note = 7377h (cs2 wait states = 3) note an NB85E500 register.
chapter 7 dmac preliminary user?s manual a13971ej7v0um 173 figure 7-28. example of two-cycle single-step transfer timing (between external srams connected to NB85E500) note these are NB85E500 signals. vbttyp1,vbttyp0 (output) vba27 to vba0 (output) vbwrite (output) vbstz (output) vbwait (input) vbahld (input) vblast (input) vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbsize1,vbsize0 (output) vdcsz7 to vdcsz0 (output) d31 to d0 (output) note rdz (output) note a25 to a0 (output) note vbseq2 to vbseq0 (output) vbclk (input) vbdc (output) dmarqn (input) dmactvn (output) dmtcon (output) wrz3 to wrz0 (output) note csz7 to csz0 (output) note vblock (output) 2h 3h 2h 0h 2h 0h 3h 2h 3h 0h 2h 3h 0h fh 0h fh 0h fh 0h 6h 6h 6h 6h 0h 0h 0h 0h 2h 2h 2h 2h fbh ffh fbh ffh fbh ffh fbh l l hi-z hi-z hi-z hi-z fh 0h 0h fh 1st 2-cycle single step transfer (3 times) 2nd 0h 0h 2h 3h 0h 2h 3h 0h 3rd fh 6h 0h 2h 6h 0h 2h fh 0h fh 0h fh ffh fbh ffh fbh ffh ffh hi-z hi-z hi-z 0h fh fh fbh ffh fbh ffh fbh ffh fbh ffh fbh ffh fbh ffh ffh
chapter 7 dmac preliminary user?s manual a13971ej7v0um 174 figure 7-29 shows an example of the timing of a two-cycle line transfer (between the external srams connected to NB85E500). the settings of the registers in this figure are as follows. [register settings] ? dbcn register = 0007h (8 transfers) ? asc register note = 0000h (no address setting wait states) ? bcc register note = 0000h (no idle states) ? dwc0 register note = 7077h (no cs2 wait states) note an NB85E500 register.
chapter 7 dmac preliminary user?s manual a13971ej7v0um 175 figure 7-29. example of two-cycle line transfer timing (between external srams connected to NB85E500) note these are NB85E500 signals. vbttyp1,vbttyp0 (output) vba27 to vba0 (output) vbwrite (output) vbstz (output) vbwait (input) vbahld (input) vblast (input) vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbsize1,vbsize0 (output) vdcsz7 to vdcsz0 (output) d31 to d0 (output) note rdz (output) note a25 to a0 (output) note vbseq2 to vbseq0 (output) vbclk (input) vbdc (output) dmarqn (input) dmactvn (output) dmtcon (output) wrz3 to wrz0 (output) note csz7 to csz0 (output) note vblock (output) 2h 2h 0h 0h fh fh fh l l hi-z hi-z hi-z fh 1st 2-cycle line transfer 0h 0h fh ffh hi-z 3h 2h 3h 2h 0h 3h 2h 3h 2nd 2h 0h 3h 2h 3h 3rd 0h 2h 0h 3h 2h 3h 0h 2h 0h 3h 2h 3h 0h 4th 5th next line transfer 0h 0h fh 0h 0h fh 0h fh 0h fh 0h fh 0h fh 0h 0h fh 6h 6h 6h 6h 6h 0h 0h 0h 0h 0h 0h 2h 2h 2h 2h 2h 6h 6h 6h 0h 0h 2h 2h 6h 6h 0h 0h 2h 2h 2h fbh ffh ffh fbh fbh ffh ffh fbh fbh ffh ffh fbh fbh ffh ffh fbh fbh ffh fbh ffh l hi-z hi-z hi-z hi-z hi-z hi-z hi-z 0h 0h fh 0h fh 0h fh 0h fh fh ffh fbh ffh ffh fbh fbh ffh ffh fbh fbh ffh ffh fbh fbh ffh ffh fbh fbh ffh fbh ffh cpu cycle
chapter 7 dmac preliminary user?s manual a13971ej7v0um 176 figure 7-30 shows an example of the timing of a two-cycle block transfer (between the external srams connected to NB85E500). the settings of the registers in this figure are as follows. [register settings] ? dbcn register = 0006h (7 transfers) ? asc register note = 0000h (no address setting wait states) ? bcc register note = 0000h (no idle states) ? dwc0 register note = 7077h (no cs2 wait states) note an NB85E500 register.
chapter 7 dmac preliminary user?s manual a13971ej7v0um 177 figure 7-30. example of two-cycle block transfer timing (between external srams connected to NB85E500) note these are NB85E500 signals. vbttyp1,vbttyp0 (output) vba27 to vba0 (output) vbwrite (output) vbstz (output) vbwait (input) vbahld (input) vblast (input) vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbsize1,vbsize0 (output) vdcsz7 to vdcsz0 (output) d31 to d0 (i/o) note rdz (output) note a25 to a0 (output) note vbseq2 to vbseq0 (output) vbclk (input) vbdc (output) dmarqn (input) dmactvn (output) dmtcon (output) wrz3 to wrz0 (output) note csz7 to csz0 (output) note vblock (output) 0h fh l l hi-z hi-z fh 1st 2-cycle block transfer (7 times) 0h fh ffh 2h 2h 0h 3h 2h 3h 2nd 4th 0h 0h 6h 6h 6h 6h 6h 0h 0h 0h 0h 0h 0h 2h 2h 2h 2h 2h 6h 6h 6h 0h 0h 2h 2h 6h 6h 0h 0h 2h 2h 2h fbh ffh fbh fbh ffh fbh fbh ffh fbh fbh ffh fbh fbh hi-z hi-z hi-z hi-z 0h 0h 0h 0h 0h ffh fbh fbh fbh ffh fbh fbh ffh fbh fbh ffh fbh fbh 2h 2h 0h 3h 2h 3h 0h 2h 2h 0h 3h 2h 3h 3rd 0h 2h 2h 0h 3h 2h 3h 0h 2h 2h 0h 3h 2h 3h 0h 2h 2h 0h 3h 2h 3h 0h 2h 2h 0h 3h 2h 3h 5th 6th 7th fh 0h fh 0h fh 0h fh 0h fh 0h fh 0h fh 0h fh 0h fh 0h fh 0h fh 0h fh 0h 0h fh 6h 6h 6h 6h 0h 2h 0h 2h 0h 2h 0h 2h fbh ffh ffh ffh fbh ffh ffh fbh ffh ffh fbh ffh fbh ffh ffh hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z fh fh 0h fh fh fh 0h fh fh ffh ffh fbh ffh ffh fbh ffh ffh fbh ffh ffh fbh fbh ffh ffh ffh
chapter 7 dmac preliminary user?s manual a13971ej7v0um 178 figure 7-31 shows an example of the timing of a two-cycle transfer (from ram connected to the vdb to sdram connected to the nu85e502). the settings of the registers in this figure are as follows. [register settings] ? dbcn register = 0001h (2 transfers) ? scrn register note = 2062h (cas latency = 2, number of wait states = 1, address shift width = 2 bits (32-bit data bus), low address width = 11 bits, address multiplexed width = 10 bits) note an nu85e502 register.
chapter 7 dmac preliminary user?s manual a13971ej7v0um 179 2. these are nu85e502 signals. figure 7-31. example of two-cycle single transfer timing (from ram connected to vdb to sdram connected to nu85e502) notes 1. these are NB85E500 signals. vbttyp1,vbttyp0 (output) vba27 to vba0 (output) vbwrite (output) vbstz (output) vbwait (input) vbahld (input) vblast (input) vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbsize1,vbsize0 (output) vdcsz7 to vdcsz0 (output) d31 to d0 (i/o) note 2 sdrasz (output) note 2 a25 to a0 (output) note 2 vbseq2 to vbseq0 (output) vbclk (input) sdclk (output) note 1 vbdc (output) dmarqn (input) dmactvn (output) dmtcon (output) sdwez (output) note 2 csz7 to csz0 (output) note 1 vblock (output) 2h 3h 0h 2h 3h ffh l l read cycle write cycle 2-cycle single transfer cpu cycle sdcasz (output) note 2 dqm3 to dqm0 (output) note 2 fh 0h iramen (output) 0h read cycle write cycle 2-cycle single transfer 0h fh 0h fh 0h fh 6h 6h 0h 0h 2h 2h l ffh bfh bfh ffh l hi-z hi-z hi-z h 0h fh ffh ffh bfh bfh ffh fh l
chapter 7 dmac preliminary user?s manual a13971ej7v0um 180 figure 7-32 shows an example of the timing of a two-cycle single transfer (from sdram connected to the nu85e502 to ram connected to the vdb). the settings of the registers in this figure are as follows. [register settings] ? dbcn register = 0001h (2 transfers) ? scrn register note = 2062h (cas latency = 2, number of wait states = 1, address shift width = 2 bits (32-bit data bus), low address width = 11 bits, address multiplexed width = 10 bits) note an nu85e502 register.
chapter 7 dmac preliminary user?s manual a13971ej7v0um 181 2. these are nu85e502 signals. figure 7-32. example of two-cycle single transfer timing (from sdram connected to nu85e502 to ram connected to vdb) notes 1. these are NB85E500 signals. vbttyp1,vbttyp0 (output) vba27 to vba0 (output) vbwrite (output) vbstz (output) vbwait (input) vbahld (input) vblast (input) vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbsize1,vbsize0 (output) vdcsz7 to vdcsz0 (output) d31 to d0 (i/o) note 2 sdrasz (output) note 2 a25 to a0 (output) note 2 vbseq2 to vbseq0 (output) vbclk (input) sdclk (output) note 1 vbdc (output) dmarqn (input) dmactvn (output) dmtcon (output) sdwez (output) note 2 csz7 to csz0 (output) note 1 vblock (output) 2h 2h ffh l l read cycle 2-cycle single transfer cpu cycle sdcasz (output) note 2 dqm3 to dqm0 (output) note 2 iramen (output) 0h 0h fh fh fh ffh ffh l hi-z h fh fh 3h 0h 3h read cycle 2-cycle single transfer l h fh 0h 0h ffh ffh ffh 6h 0h 0h 2h bfh bfh write cycle 0h 6h 0h 2h hi-z hi-z bfh write cycle bfh
chapter 7 dmac preliminary user?s manual a13971ej7v0um 182 (2) flyby transfers figures 7-33 to 7-38 show examples of the timing of flyby transfers between external sram and external i/o connected to the memc (NB85E500). the flyby transfer consists of the following states. ? t1, t2 states: these are basic states for accessing the NB85E500. ? t3 state: this is a basic state added for flyby transfer. ? ta state: this is an address setting wait state inserted by means of a setting in the NB85E500?s asc register. ? ti state: this is an idle state inserted by means of a setting in the NB85E500?s bcc register. ? tw state: this is a wait state inserted by means of a setting in the NB85E500?s dwc0 register. remarks 1. the levels of the broken-line portions of the vbttyp1, vbttyp0, vba27 to vba0, vbd31 to vbd0, vbctyp2 to vbctyp0, vbseq2 to vbseq0, vbsize1, vbsize0, vbwait, vbahld, and vblast signals indicate the undefined state (weak unknown) entered when the NB85E internal bus holder is driving. the levels of the broken-line portions of the a25 to a0 signals are undefined. 2. n = 3 to 0 figure 7-33 shows an example of the timing of a flyby single transfer (from external sram to external i/o connected to NB85E500). the settings of the registers in this figure are as follows. [register settings] ? dbcn register = 0001h (2 transfers) ? asc register note = ffefh (cs2 address setting wait states = 2) ? bcc register note = ffefh (cs2 idle states = 2) ? dwc0 register note = 7377h (cs2 wait states = 3) note an NB85E500 register.
chapter 7 dmac preliminary user?s manual a13971ej7v0um 183 figure 7-33. example of flyby single transfer timing (from external sram to external i/o connected to NB85E500) note these are NB85E500 signals. vbttyp1,vbttyp0 (output) vba27 to vba0 (output) vbwrite (output) vbstz (output) vbwait (input) vbahld (input) vblast (input) vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbsize1,vbsize0 (output) vdcsz7 to vdcsz0 (output) d31 to d0 (i/o) note rdz (output) note a25 to a0 (output) note vbseq2 to vbseq0 (output) vbclk (input) vbdc (output) dmarqn (input) dmactvn (output) dmtcon (output) wrz3 to wrz0 (output) note csz7 to csz0 (output) note vblock (output) 0h 2h 3h 2h fh fh ffh ffh l l hi-z fh ffh ffh ta 1st 2h 3h t1 tw t2 t3 ti ta t1 tw t2 t3 ti 2nd cpu cycle 0h l 0h 0h fh 7h 0h 2h 7h 0h 2h l fbh fbh ffh iordz (output) note iowrz (output) note h hi-z hi-z fbh fbh ffh
chapter 7 dmac preliminary user?s manual a13971ej7v0um 184 figure 7-34 shows an example of the timing of a flyby single-step transfer (from external sram to external i/o connected to NB85E500). the settings of the registers in this figure are as follows. [register settings] ? dbcn register = 0001h (2 transfers) ? asc register note = ffefh (cs2 address setting wait states = 2) ? bcc register note = ffefh (cs2 idle states = 2) ? dwc0 register note = 7377h (cs2 wait states = 3) note an NB85E500 register.
chapter 7 dmac preliminary user?s manual a13971ej7v0um 185 figure 7-34. example of flyby single-step transfer timing (from external sram to external i/o connected to NB85E500) note these are NB85E500 signals. vbttyp1,vbttyp0 (output) vba27 to vba0 (output) vbwrite (output) vbstz (output) vbwait (input) vbahld (input) vblast (input) vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbsize1,vbsize0 (output) vdcsz7 to vdcsz0 (output) d31 to d0 (i/o) note rdz (output) note a25 to a0 (output) note vbseq2 to vbseq0 (output) vbclk (input) vbdc (output) dmarqn (input) dmactvn (output) dmtcon (output) w rz3 to wrz0 (output) note csz7 to csz0 (output) note vblock (output) 0h 2h 3h 2h fh fh ffh ffh l l hi-z fh ffh ffh ta 1st 2h 3h t1 tw t2 t3 ti ta t1 tw t2 t3 ti 2nd cpu cycle 0h l 0h 0h fh 7h 0h 2h 7h 0h 2h l fbh fbh ffh iordz (output) note iowrz (output) note h hi-z hi-z fbh fbh ffh
chapter 7 dmac preliminary user?s manual a13971ej7v0um 186 figure 7-35 shows an example of the timing of a flyby single-step transfer (from external i/o to external sram connected to NB85E500). the settings of the registers in this figure are as follows. [register settings] ? dbcn register = 0001h (2 transfers) ? asc register note = ffefh (cs2 address setting wait states = 2) ? bcc register note = ffefh (cs2 idle states = 2) ? dwc0 register note = 7377h (cs2 wait states = 3) note an NB85E500 register.
chapter 7 dmac preliminary user?s manual a13971ej7v0um 187 figure 7-35. example of flyby single-step transfer timing (from external i/o to external sram connected to NB85E500) note these are NB85E500 signals. vbttyp1,vbttyp0 (output) vba27 to vba0 (output) vbwrite (output) vbstz (output) vbwait (input) vbahld (input) vblast (input) vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbsize1,vbsize0 (output) vdcsz7 to vdcsz0 (output) d31 to d0 (i/o) note rdz (output) note a25 to a0 (output) note vbseq2 to vbseq0 (output) vbclk (input) vbdc (output) dmarqn (input) dmactvn (output) dmtcon (output) wrz3 to wrz0 (output) note csz7 to csz0 (output) note vblock (output) 0h 2h 3h 2h fh fh ffh ffh l l hi-z ffh ffh ta 1st 2h 3h t1 tw t2 t3 ti ta t1 tw t2 t3 ti 2nd cpu cycle 0h l 0h 0h fh 7h 0h 2h 7h 0h 2h l fbh fbh ffh iordz (output) note iowrz (output) note h hi-z fbh fbh ffh hi-z h fh 0h 0h fh fh
chapter 7 dmac preliminary user?s manual a13971ej7v0um 188 figure 7-36 shows an example of the timing of a flyby line transfer (from external sram to external i/o connected to NB85E500). the settings of the registers in this figure are as follows. [register settings] ? dbcn register = 0007h (8 transfers) ? asc register note = 0000h (no address setting wait states) ? bcc register note = 0000h (no idle states) ? dwc0 register note = 0000h (no wait states) note an NB85E500 register.
chapter 7 dmac preliminary user?s manual a13971ej7v0um 189 figure 7-36. example of flyby line transfer timing (from external sram to external i/o connected to NB85E500) note these are NB85E500 signals. vbttyp1,vbttyp0 (output) vba27 to vba0 (output) vbwrite (output) vbstz (output) vbwait (input) vbahld (input) vblast (input) vbd31 to vbd0 (i/o) vbbenz3-vbbenz0 (output) vbctyp2-vbctyp0 (output) vbsize1,vbsize0 (output) vdcsz7 to vdcsz0 (output) d31 to d0 (i/o) note rdz (output) note a25 to a0 (output) note vbseq2 to vbseq0 (output) vbclk (input) vbdc (output) dmarqn (input) dmactvn (output) dmtcon (output) wrz3 to wrz0 (output) note csz7 to csz0 (output) note vblock (output) 0h fh ffh l l hi-z fh ffh 1st t1 t2 t3 l 7h fbh iordz (output) note iowrz (output) note h 2h 2h 3h fbh 2nd t1 t2 t3 0h fh 0h 0h 2h ffh hi-z ffh 0h 3rd t1 t2 t3 2h 2h 3h 2h 2h 3h fh 0h 0h 7h 0h 2h 7h 0h 2h hi-z fbh ffh fbh 4th t1 t2 t3 0h 2h 2h 3h fh 0h 7h 0h 2h hi-z ffh fbh 5th t1 t2 t3 2h 2h 3h fh 0h 7h 0h 2h 6th t1 t2 t3 7th t1 t2 t3 8th t1 t2 t3 0h 2h 2h 3h fh 0h 7h 0h 2h 0h 2h 2h 3h fh 0h 7h 0h 2h 0h 2h 2h 3h fh 0h 7h 0h 2h 0h hi-z hi-z hi-z hi-z hi-z fbh ffh fbh ffh fbh ffh fbh ffh fbh ffh fbh ffh fbh ffh ffh fbh ffh fbh ffh fbh ffh fbh ffh 0h cpu cycle fh flyby line transfer flyby line transfer
chapter 7 dmac preliminary user?s manual a13971ej7v0um 190 figure 7-37 shows an example of the timing of a flyby block transfer (from external sram to external i/o connected to NB85E500). the settings of the registers in this figure are as follows. [register settings] ? dbcn register = 0007h (8 transfers) ? asc register note = 0000h (no address setting wait states) ? bcc register note = 0000h (no idle states) ? dwc0 register note = 0000h (no wait states) note an NB85E500 register.
chapter 7 dmac preliminary user?s manual a13971ej7v0um 191 figure 7-37. example of flyby block transfer timing (from external sram to external i/o connected to NB85E500) note these are NB85E500 signals. vbttyp1,vbttyp0 (output) vba27 to vba0 (output) vbwrite (output) vbstz (output) vbwait (input) vbahld (input) vblast (input) vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbsize1,vbsize0 (output) vdcsz7 to vdcsz0 (output) d31 to d0 (i/o) note rdz (output) note a25 to a0 (output) note vbseq2 to vbseq0 (output) vbclk (input) vbdc (output) dmarqn (input) dmactvn (output) dmtcon (output) wrz3 to wrz0 (output) note csz7 to csz0 (output) note vblock (output) 0h fh ffh l l hi-z fh ffh 1st t1 t2 t3 l 0h fh 7h l fbh ffh iordz (output) note iowrz (output) note h ffh 2nd t1 t2 t3 3rd t1 t2 t3 4th t1 t2 t3 5th t1 t2 t3 6th t1 t2 t3 7th t1 t2 t3 8th t1 t2 t3 2h 2h 3h 2h 2h 3h 2h 2h 3h 2h 2h 3h 2h 2h 3h 2h 2h 3h 2h 2h 3h 2h 2h 3h 0h 0h 2h hi-z fbh hi-z hi-z hi-z hi-z hi-z hi-z hi-z
chapter 7 dmac preliminary user?s manual a13971ej7v0um 192 figure 7-38 shows an example of the timing of a flyby block transfer (from external i/o to external sram connected to NB85E500). the settings of the registers in this figure are as follows. [register settings] ? dbcn register = 0007h (8 transfers) ? asc register note = 0000h (no address setting wait states) ? bcc register note = 0000h (no idle states) ? dwc0 register note = 0000h (no wait states) note an NB85E500 register.
chapter 7 dmac preliminary user?s manual a13971ej7v0um 193 figure 7-38. example of flyby block transfer timing (from external i/o to external sram connected to NB85E500) note these are NB85E500 signals. vbttyp1,vbttyp0 (output) vba27 to vba0 (output) vbwrite (output) vbstz (output) vbwait (input) vbahld (input) vblast (input) vbd31 to vbd0 (i/o) vbbenz3 to vbbenz0 (output) vbctyp2 to vbctyp0 (output) vbsize1,vbsize0 (output) vdcsz7 to vdcsz0 (output) d31 to d0 (i/o) note rdz (output) note a25 to a0 (output) note vbseq2 to vbseq0 (output) vbclk (input) vbdc (output) dmarqn (input) dmactvn (output) dmtcon (output) wrz3 to wrz0 (output) note csz7 to csz0 (output) note vblock (output) 0h fh ffh l l hi-z ffh 1st t1 t2 t3 l 0h fh 7h l fbh ffh iordz (output) note iowrz (output) note h ffh 2nd t1 t2 t3 3rd t1 t2 t3 4th t1 t2 t3 5th t1 t2 t3 6th t1 t2 t3 7th t1 t2 t3 8th t1 t2 t3 2h 2h 3h 2h 2h 3h 2h 2h 3h 2h 2h 3h 2h 2h 3h 2h 2h 3h 2h 2h 3h 2h 2h 3h 0h 0h 2h hi-z fbh hi-z hi-z hi-z hi-z hi-z hi-z hi-z h 0h fh fh fh fh fh fh fh fh fh 0h 0h 0h 0h 0h 0h 0h
chapter 7 dmac preliminary user?s manual a13971ej7v0um 194 7.15 precautions (1) memory boundary operation is not guaranteed if the address of the transfer source or transfer destination is outside of the area for the dma object (external memory, ram, or peripheral macro) during a dma transfer. (2) misalign data transfer dma transfer of misalign data with a 32-bit or 16-bit bus width is not supported. (3) intervals related to dma transfer the overhead before a dma transfer and the minimum number of clocks required for a dma transfer are shown below. ? from the acknowledgement of the dmarqn signal until the rising edge of the dmactvn signal (n = 3 to 0): 3 clocks ? access to ram connected to vdb: 2 clocks in the case of external memory access, these depend on the connected memc and the external memory. an example is shown below. example when sram is accessed using the memc (NB85E500/nu85e500) transfer type conditions transfer mode minimum clock number single 5 clocks single-step 5 clocks ? time between start of read cycle and end of write cycle ? the transfer time of one transfer for single and single-step transfers, and four transfers for a line transfer. ? the combinations of transfer sources and destinations are as follows. vsb vsb vsb ram ram vsb ram ram line 32 clocks single 6 clocks single-step 4 clocks 2-cycle time in which bus is released to cpu line 6 clocks flyby transfer time of one transfer from sram to i/o, and from i/o to sram ? 3 clocks (4) bus arbitration for the cpu the cpu can access external memory, peripheral macros, or ram for which no dma transfer is being performed. if a data transfer is being performed within external memory or a peripheral macro, the cpu can access ram. also, if a data transfer is being performed between on-chip ram and ram, the cpu can access external memory or a peripheral macro.
chapter 7 dmac preliminary user?s manual a13971ej7v0um 195 (5) dma transfer end interrupt the dma transfer end interrupt is not generated when dma transfer is complete. if the generation of an interrupt coinciding with the completion of transfer is required, input the dmatcon signal to the intm pin and perform maskable interrupt servicing (n = 3 to 0, m = 63 to 0).
preliminary user?s manual a13971ej7v0um 196 chapter 8 intc the interrupt control unit (intc), which can process interrupt requests generated for a total of 67 sources, processes various types of interrupt requests from external sources. in addition, exception processing can be started (exception trap) due to a trap instruction (software exception) or due to the generation of an exception event (fetching of an illegal opcode). an interrupt is an event that is generated independently of program execution, and an exception is an event that is generated dependent on program execution. generally, the processing of an exception takes precedence over the processing of an interrupt. 8.1 features ? interrupt non-maskable interrupt: 3 sources maskable interrupt: 64 sources 8 levels programmable priorities (maskable interrupt) multiple interrupt control according to priority mask specification to each maskable interrupt request ? exception software exception: 32 sources exception trap: 1 source (illegal opcode exception) these interrupt/exception sources are listed in table 8-1. table 8-1. interrupt/exception list (1/3) interrupt/exception source type classifi- cation name control register generating source default priority exception code handler address restored pc reset interrupt reset ? dcresz input ? 0000h 00000000h undefined non-maskable interrupt nmi0 ? dcnmi0 input ? 0010h 00000010h nextpc interrupt nmi1 ? dcnmi1 input ? 0020h 00000020h nextpc interrupt nmi2 ? dcnmi2 input ? 0030h 00000030h nextpc exception trap0n note ?trap instruction ? 004nh 00000040h nextpc software exception exception trap1n note ?trap instruction ? 005nh 00000050h nextpc exception trap exception ilgop ? illegal opcode ? 0060h 00000060h nextpc maskable interrupt int0 pic0 int0 input 0 0080h 00000080h nextpc interrupt int1 pic1 int1 input 1 0090h 00000090h nextpc interrupt int2 pic2 int2 input 2 00a0h 000000a0h nextpc interrupt int3 pic3 int3 input 3 00b0h 000000b0h nextpc interrupt int4 pic4 int4 input 4 00c0h 000000c0h nextpc interrupt int5 pic5 int5 input 5 00d0h 000000d0h nextpc interrupt int6 pic6 int6 input 6 00e0h 000000e0h nextpc note n: value of 0 to fh
chapter 8 intc preliminary user?s manual a13971ej7v0um 197 table 8-1. interrupt/exception list (2/3) interrupt/exception source type classifi- cation name control register generating source default priority exception code handler address restored pc maskable interrupt int7 pic7 int7 input 7 00f0h 000000f0h nextpc interrupt int8 pic8 int8 input 8 0100h 00000100h nextpc interrupt int9 pic9 int9 input 9 0110h 00000110h nextpc interrupt int10 pic10 int10 input 10 0120h 00000120h nextpc interrupt int11 pic11 int11 input 11 0130h 00000130h nextpc interrupt int12 pic12 int12 input 12 0140h 00000140h nextpc interrupt int13 pic13 int13 input 13 0150h 00000150h nextpc interrupt int14 pic14 int14 input 14 0160h 00000160h nextpc interrupt int15 pic15 int15 input 15 0170h 00000170h nextpc interrupt int16 pic16 int16 input 16 0180h 00000180h nextpc interrupt int17 pic17 int17 input 17 0190h 00000190h nextpc interrupt int18 pic18 int18 input 18 01a0h 000001a0h nextpc interrupt int19 pic19 int19 input 19 01b0h 000001b0h nextpc interrupt int20 pic20 int20 input 20 01c0h 000001c0h nextpc interrupt int21 pic21 int21 input 21 01d0h 000001d0h nextpc interrupt int22 pic22 int22 input 22 01e0h 000001e0h nextpc interrupt int23 pic23 int23 input 23 01f0h 000001f0h nextpc interrupt int24 pic24 int24 input 24 0200h 00000200h nextpc interrupt int25 pic25 int25 input 25 0210h 00000210h nextpc interrupt int26 pic26 int26 input 26 0220h 00000220h nextpc interrupt int27 pic27 int27 input 27 0230h 00000230h nextpc interrupt int28 pic28 int28 input 28 0240h 00000240h nextpc interrupt int29 pic29 int29 input 29 0250h 00000250h nextpc interrupt int30 pic30 int30 input 30 0260h 00000260h nextpc interrupt int31 pic31 int31 input 31 0270h 00000270h nextpc interrupt int32 pic32 int32 input 32 0280h 00000280h nextpc interrupt int33 pic33 int33 input 33 0290h 00000290h nextpc interrupt int34 pic34 int34 input 34 02a0h 000002a0h nextpc interrupt int35 pic35 int35 input 35 02b0h 000002b0h nextpc interrupt int36 pic36 int36 input 36 02c0h 000002c0h nextpc interrupt int37 pic37 int37 input 37 02d0h 000002d0h nextpc interrupt int38 pic38 int38 input 38 02e0h 000002e0h nextpc interrupt int39 pic39 int39 input 39 02f0h 000002f0h nextpc interrupt int40 pic40 int40 input 40 0300h 00000300h nextpc interrupt int41 pic41 int41 input 41 0310h 00000310h nextpc interrupt int42 pic42 int42 input 42 0320h 00000320h nextpc interrupt int43 pic43 int43 input 43 0330h 00000330h nextpc
chapter 8 intc preliminary user?s manual a13971ej7v0um 198 table 8-1. interrupt/exception list (3/3) interrupt/exception source type classifi- cation name control register generating source default priority exception code handler address restored pc maskable interrupt int44 pic44 int44 input 44 0340h 00000340h nextpc interrupt int45 pic45 int45 input 45 0350h 00000350h nextpc interrupt int46 pic46 int46 input 46 0360h 00000360h nextpc interrupt int47 pic47 int47 input 47 0370h 00000370h nextpc interrupt int48 pic48 int48 input 48 0380h 00000380h nextpc interrupt int49 pic49 int49 input 49 0390h 00000390h nextpc interrupt int50 pic50 int50 input 50 03a0h 000003a0h nextpc interrupt int51 pic51 int51 input 51 03b0h 000003b0h nextpc interrupt int52 pic52 int52 input 52 03c0h 000003c0h nextpc interrupt int53 pic53 int53 input 53 03d0h 000003d0h nextpc interrupt int54 pic54 int54 input 54 03e0h 000003e0h nextpc interrupt int55 pic55 int55 input 55 03f0h 000003f0h nextpc interrupt int56 pic56 int56 input 56 0400h 00000400h nextpc interrupt int57 pic57 int57 input 57 0410h 00000410h nextpc interrupt int58 pic58 int58 input 58 0420h 00000420h nextpc interrupt int59 pic59 int59 input 59 0430h 00000430h nextpc interrupt int60 pic60 int60 input 60 0440h 00000440h nextpc interrupt int61 pic61 int61 input 61 0450h 00000450h nextpc interrupt int62 pic62 int62 input 62 0460h 00000460h nextpc interrupt int63 pic63 int63 input 63 0470h 00000470h nextpc remarks 1. default priority: priority that takes precedence when two or more maskable interrupt requests with the same priority level occur at the same time. the highest priority is 0. restored pc: this is the pc value saved in eipc or fepc upon activation of interrupt servicing or exception processing. note, however, that the restored pc when a non-maskable or maskable interrupt is acknowledged while one of the following instructions is being executed does not become the nextpc (if an interrupt is acknowledged during interrupt execution, execution stops, and then resumes after the interrupt servicing has finished). ? load instructions (sld.b, sld.bu, sld.h, sld.hu, sld.w) ? division instructions (div, divh, divu, divhu) ? prepare, dispose instructions (only if an interrupt is generated before the stack pointer is updated) nextpc: the pc value that starts the processing following the completion of interrupt/exception processing. 2. the execution address of the illegal instruction when an illegal opcode exception occurs is calculated as follows: (restored pc ? 4)
chapter 8 intc preliminary user?s manual a13971ej7v0um 199 8.2 non-maskable interrupts (nmi) a non-maskable interrupt request (nmi) is acknowledged unconditionally even if the NB85E is in an interrupt disabled (di) state. a non-maskable interrupt request is generated according to dcnmin pin input (n = 2 to 0). when a rising edge is input to the dcnmin pin, a non-maskable interrupt (nmin) is generated. if multiple non-maskable interrupts are generated at the same time, the highest priority servicing is executed according to the following priority order (the lower priority interrupts are ignored). nmi2 > nmi1 > nmi0 note that if an nmi0, nmi1, or nmi2 request is generated while nmi0 is being serviced, the servicing is executed as follows. (1) if an nmi0 request is generated while nmi0 is being serviced the new nmi0 request is held pending regardless of the value of the psw?s np bit. the pending nmi0 request is acknowledged after servicing of the current nmi0 request has finished (after execution of the reti instruction). (2) if an nmi1 request is generated while nmi0 is being serviced if the psw?s np bit remains set (1) while nmi0 is being serviced, the new nmi1 request is held pending. the pending nmi1 request is acknowledged after servicing of the current nmi0 request has finished (after execution of the reti instruction). if the psw?s np bit is cleared (0) while nmi0 is being serviced, the newly generated nmi1 request is executed (nmi0 servicing is halted). (3) if an nmi2 request is generated while nmi0 is being serviced the new nmi2 request is executed, regardless of the value of the psw?s np bit (nmi0 servicing is halted). caution although the values of the pc and psw are saved to an nmi status save register (fepc, fepsw) when a non-maskable interrupt (nmi) request is generated, only nmi0 can be restored by the reti instruction at this time. because nmi1 and nmi2 cannot be restored by the reti instruction, the system must be reset after servicing these interrupts.
chapter 8 intc preliminary user?s manual a13971ej7v0um 200 figure 8-1. example of non-maskable interrupt request acknowledgement operation (1/2) (a) multiple nmi requests generated at the same time ? nmi0 and nmi1 requests generated simultaneously ? nmi0 and nmi2 requests generated simultaneously ? nmi1 and nmi2 requests generated simultaneously ? nmi0, nmi1, and nmi2 requests generated simultaneously main routine nmi0 and nmi2 requests (generated simultaneously) nmi2 servicing system reset main routine nmi1 and nmi2 requests (generated simultaneousl y) nmi2 servicing system reset nmi0 and nmi1 requests (generated simultaneously) main routine nmi1 servicing system reset main routine nmi0, nmi1, and nmi2 requests (generated simultaneously) nmi2 servicing system reset
chapter 8 intc preliminary user?s manual a13971ej7v0um 201 main routine nmi0 request nmi1 request nmi0 servicing (held pending) system reset nmi1 servicing figure 8-1. example of non-maskable interrupt request acknowledgement operation (2/2) (b) nmi request generated during nmi servicing nmi request generated during nmi servicing nmi being serviced nmi0 nmi1 nmi2 nmi0 ? nmi0 request generated during nmi0 servicing ? nmi1 request generated during nmi0 servicing (np = 1 retained before nmi1 request) ? nmi1 request generated during nmi0 servicing (np = 0 set before nmi1 request) ? nmi2 request generated during nmi0 servicing nmi1 ? nmi0 request generated during nmi1 servicing ? nmi1 request generated during nmi1 servicing ? nmi2 request generated during nmi1 servicing nmi2 ? nmi0 request generated during nmi2 servicing ? nmi1 request generated during nmi2 servicing ? nmi2 request generated during nmi2 servicing main routine nmi0 request nmi0 request nmi0 servicing (held pending) servicing of pending nmi0 main routine nmi0 request nmi2 request nmi0 servicing nmi2 servicing system reset main routine nmi1 request nmi0 request nmi1 servicing (invalid) system reset main routine nmi1 request nmi1 request nmi1 servicing (invalid) system reset main routine nmi2 request nmi0 request nmi2 servicing (invalid) system reset main routine nmi2 request nmi1 request nmi2 servicing (invalid) system reset main routine nmi2 request nmi2 request nmi2 servicing (invalid) system reset ? nmi1 request generated during nmi0 servicing (np = 0 set after nmi1 request) main routine nmi0 request nmi1 request nmi0 servicing nmi1 servicing system reset np = 0 main routine nmi0 request nmi1 request nmi0 servicing nmi1 servicing system reset np = 0 (held pending) main routine nmi1 request nmi2 request nmi1 servicing nmi2 servicing system reset
chapter 8 intc preliminary user?s manual a13971ej7v0um 202 8.2.1 operation if a non-maskable interrupt is generated according to dcnmin input, the cpu performs the following processing and shifts control to the handler routine (n = 2 to 0). <1> save the restored pc in the fepc. <2> save the current psw in the fepsw. <3> write the exception code in the higher halfword (fecc) of the ecr. <4> set the np and id bits of the psw and clear the ep bit. <5> set the handler address for the non-maskable interrupt in the pc and shift control. figure 8-2 shows the processing format of non-maskable interrupt service. figure 8-2. non-maskable interrupt processing format non-maskable interrupt request fepc restored pc fepsw psw ecr.fecc exception code psw.np 1 psw.ep 0 psw.id 1 pc handler address 0 psw.np intc acknowledgement cpu processing 1 dcnmin input interrupt service interrupt request pending
chapter 8 intc preliminary user?s manual a13971ej7v0um 203 8.2.2 restore (1) nmi0 control is returned from nmi0 servicing according to the reti instruction. when the reti instruction is executed, the cpu performs the following processing and shifts control to the restored pc address. <1> since the ep bit of the psw is 0 and the np bit is 1, fetch the restored pc and psw from the fepc and fepsw. <2> shift control to the fetched restored pc address and psw status. figure 8-3 shows the processing format of the reti instruction. figure 8-3. reti instruction processing format 0 psw.ep pc eipc psw eipsw 1 psw.np 0 1 pc fepc psw fepsw reti instruction original processing restored caution if the psw.ep bit or psw.np bit is changed by the ldsr instruction during nmi0 servicing, then in order to restore the pc and psw correctly when control is returned according to the reti instruction, the ldsr instruction must be used to return psw.ep to 0 and psw.np to 1 immediately before executing the reti instruction. remark the solid line indicates the cpu processing flow. (2) nmi1, nmi2 restoring by reti instruction is not possible. perform a system reset according to dcresz input after interrupt servicing.
chapter 8 intc preliminary user?s manual a13971ej7v0um 204 8.3 maskable interrupts a maskable interrupt request is an interrupt request for which the acknowledgement of the interrupt can be masked according to the interrupt control register. there are 64 interrupt sources for maskable interrupts. a maskable interrupt request is generated according to intn pin input (n = 63 to 0). when a rising edge is input to the intn pin, a maskable interrupt (intn) is generated. if multiple maskable interrupt requests are generated at the same time, their priorities are determined according to the default priorities. in addition to the default priority, eight interrupt priority levels can be set according to the interrupt control register (programmable priority control). when an interrupt request is acknowledged, interrupt disabled (di) state is set, and the acknowledgement of subsequent maskable interrupt requests is prohibited. if the ei instruction is executed during an interrupt service routine, interrupt enabled (ei) state is set, and the acknowledgement of interrupt requests having higher priorities than the priority level of the currently acknowledged interrupt request (specified by the interrupt control register) is permitted. interrupts having the same priority level cannot be nested. however, the following processing is required for multiple interrupt service. <1> save the eipc and eipsw in memory or general-purpose registers before executing the ei instruction. <2> before executing the reti instruction, execute the di instruction and return the values that were saved in step <1> to the eipc and eipsw. 8.3.1 operation if a maskable interrupt is generated according to intn input, the cpu performs the following processing and shifts control to the handler routine. <1> save the restored pc in the eipc. <2> save the current psw in the eipsw. <3> write the exception code in the lower halfword (eicc) of the ecr. <4> set the id bit of the psw and clear the ep bit. <5> set the handler address for the interrupt in the pc and shift control. an intn input that is masked by the intc and an intn input that was generated while another interrupt was being serviced (psw.np = 1 or psw.id = 1) are kept pending within the intc. in this case, if the mask is canceled or the reti and ldsr instructions are used to set psw.np to 0 and psw.id to 0, the new maskable interrupt service is started according to the intn input that had been pending. figure 8-4 shows the processing format of maskable interrupt service.
chapter 8 intc preliminary user?s manual a13971ej7v0um 205 figure 8-4. maskable interrupt processing format interrupt request? intc acknowledgement yes no interrupt unmasked? no yes priority higher than that of interrupt currently processed? no yes priority higher than that of other interrupt request? no yes highest default priority of interrupt requests with same priority? no yes psw.np 0 psw.id 1 1 eipc restored pc eipsw psw ecr.eicc exception code psw.ep 0 psw.id 1 pc handler address 0 cpu processing interrupt service interrupt service pending interrupt request pending maskable interrupt request intn input
chapter 8 intc preliminary user?s manual a13971ej7v0um 206 8.3.2 restore control is returned from maskable interrupt service according to the reti instruction. when the reti instruction is executed, the cpu performs the following processing and shifts control to the restored pc address. <1> since the ep bit of the psw is 0 and the np bit is 0, fetch the restored pc and psw from the eipc and eipsw. <2> shift control to the fetched restored pc address and psw status. figure 8-5 shows the processing format of the reti instruction. figure 8-5. reti instruction processing format 0 psw.ep pc eipc psw eipsw 1 psw.np 0 1 pc fepc psw fepsw reti instruction original processing restored caution if the psw.ep bit and psw.np bit are changed by the ldsr instruction during maskable interrupt service, then in order to restore the pc and psw correctly when control is returned according to the reti instruction, the ldsr instruction must be used to return psw.ep to 0 and psw.np to 0 immediately before executing the reti instruction. remark the solid line indicates the cpu processing flow.
chapter 8 intc preliminary user?s manual a13971ej7v0um 207 8.3.3 maskable interrupt priorities the intc provides multiple interrupt service that acknowledges another interrupt while an interrupt is being serviced. multiple interrupts can be controlled according to priorities. priority control includes control according to default priorities and programmable priority control according to the interrupt control register (picn). for priority control according to default priorities, if multiple interrupts having the same priority level according to the picn register are generated at the same time, the interrupts are serviced according to the priorities (default priorities) that have been assigned in advance to each interrupt request (see table 8-1 interrupt/exception list ). for programmable priority control, the interrupt requests are divided into eight levels according to picn register settings. when an interrupt is acknowledged, the id flag of the psw is automatically set (1). therefore, to use multiple interrupt service, clear (0) the id flag (such as by executing the ei instruction during the interrupt service program) to set the interrupt enable state.
chapter 8 intc preliminary user?s manual a13971ej7v0um 208 figure 8-6. processing example in which another interrupt request is issued during interrupt servicing (1/2) remarks 1. to in the figure represent dummy names that are assigned to distinguish between the interrupt requests. 2. higher or lower default priorities mentioned in the figure indicate relative priorities between two interrupt requests. caution to use multiple interrupt servicing, the contents of the eipc and eipsw registers must be saved. main routine servicing of servicing of interrupt request is acknowledged because the priority of is higher than that of and interrupts are enabled. ei interrupt request (level 3) ei interrupt request (level 3) servicing of servicing of although the priority of interrupt request is higher than that of , is held pending because interrupts are disabled. interrupt request (level 2) servicing of servicing of interrupt request is held pending even if interrupts are enabled because its priority is lower than that of . ei interrupt request (level 1) servicing of servicing of interrupt request is held pending even if interrupts are enabled because its priority is the same as that of . ei interrupt request (level 2) interrupt request (level 2) interrupt request (level 3) interrupt request (level 1)
chapter 8 intc preliminary user?s manual a13971ej7v0um 209 figure 8-6. processing example in which another interrupt request is issued during interrupt servicing (2/2) notes 1. default priority is lower. 2. default priority is higher. interrupt request (level 2) servicing of servicing of servicing of servicing of main routine interrupt request (level 2) interrupt request is held pending because its priority is lower than that of . interrupt request that occurs after is acknowledged because it has the higher priority. servicing of interrupt request (level 1) ei ei servicing of interrupt request (level 3) interrupt request (level 3) interrupt request (level 1) interrupt request (level 3) servicing of ei servicing of
ei servicing of ei servicing of ei interrupt request (level 1) servicing of servicing of servicing of interrupt request (level 2 note 1 ) interrupt request (level 2 note 2 ) interrupt requests and are held pending because servicing of is performed in the interrupt disabled status. pending interrupt requests are acknowledged after servicing of interrupt request . at this time, interrupt request is acknowledged first even though has occurred first because the priority of is higher than that of . if levels 3 to 0 are acknowledged pending interrupt requests and are acknowledged after servicing of . because the priorities of and are the same, is acknowledged first according to the default priority, regardless of the order in which the interrupt requests have been generated. interrupt request
(level 2) interrupt request (level 1) interrupt request (level 0)
chapter 8 intc preliminary user?s manual a13971ej7v0um 210 figure 8-7. processing example for simultaneously issued interrupt requests remark to in the figure represent dummy names that are assigned to distinguish between the interrupt requests. interrupt request (level 2), interrupt request (level 1), interrupt request (level 1) servicing of servicing of servicing of main routine ei default priority: a > b > c interrupt requests and are acknowledged first according to their priorities. because the priorities of and are the same, is acknowledged first because it has the higher default priority.
chapter 8 intc preliminary user?s manual a13971ej7v0um 211 8.3.4 control registers (1) interrupt control registers 0 to 63 (pic0 to pic63) the interrupt control registers, which are assigned to each interrupt request (maskable interrupt), set control conditions for each interrupt. these registers can be read or written in 8-bit or 1-bit units. figure 8-8. interrupt control registers 0 to 63 (pic0 to pic63) 76543210 picn pifn pmkn 0 0 0 pprn2 pprn1 pprn0 address fffff110h to after reset 47h fffff18eh bit position bit name function 7 pifn this is the interrupt request flag. 0: no interrupt request issued 1: interrupt request issued when the interrupt request is acknowledged, this is automatically cleared (0). 6 pmkn this is the interrupt mask flag. 0: interrupt service enabled 1: interrupt service disabled (pending) 2 to 0 pprn2 to pprn0 specifies eight priority levels for each interrupt. pprn2 pprn1 pprn0 interrupt priority 0 0 0 specifies level 0 (highest) 0 0 1 specifies level 1 0 1 0 specifies level 2 0 1 1 specifies level 3 1 0 0 specifies level 4 1 0 1 specifies level 5 1 1 0 specifies level 6 1 1 1 specifies level 7 (lowest) remark n = 0 to 63
chapter 8 intc preliminary user?s manual a13971ej7v0um 212 (2) interrupt mask registers 0 to 3 (imr0 to imr3) the interrupt mask registers maintain the mask status of each maskable interrupt. the pmkn bit of this register and the pmkn bit of the picn register are linked (n = 0 to 63). the imrm register can be read or written in 16-bit units (m = 0 to 3). when using the higher 8 bits of the imrm register as the imrmh register, and the lower 8 bits as the imrml register, the imrm register can be read or written in 8-bit or 1-bit units. figure 8-9. interrupt mask registers 0 to 3 (imr0 to imr3) 1514131211109876543210 imr0 pmk 15 pmk 14 pmk 13 pmk 12 pmk 11 pmk 10 pmk 9 pmk 8 pmk 7 pmk 6 pmk 5 pmk 4 pmk 3 pmk 2 pmk 1 pmk 0 address fffff100h after reset ffffh imr1 pmk 31 pmk 30 pmk 29 pmk 28 pmk 27 pmk 26 pmk 25 pmk 24 pmk 23 pmk 22 pmk 21 pmk 20 pmk 19 pmk 18 pmk 17 pmk 16 address fffff102h after reset ffffh imr2 pmk 47 pmk 46 pmk 45 pmk 44 pmk 43 pmk 42 pmk 41 pmk 40 pmk 39 pmk 38 pmk 37 pmk 36 pmk 35 pmk 34 pmk 33 pmk 32 address fffff104h after reset ffffh imr3 pmk 63 pmk 62 pmk 61 pmk 60 pmk 59 pmk 58 pmk 57 pmk 56 pmk 55 pmk 54 pmk 53 pmk 52 pmk 51 pmk 50 pmk 49 pmk 48 address fffff106h after reset ffffh
chapter 8 intc preliminary user?s manual a13971ej7v0um 213 (3) in-service priority register (ispr) this register maintains the priority level of the maskable interrupt that is being acknowledged. when an interrupt request is acknowledged, the bit corresponding to the priority level of that interrupt request is set (1) and maintained while the interrupt is being serviced. when the reti instruction is executed, the bit corresponding to the interrupt request having the highest priority among the bits that are set (1) within the ispr register is automatically cleared (0). however, it is not cleared (0) when control returns from non-maskable interrupt service or exception processing. this register is read-only in 8-bit or 1-bit units. figure 8-10. in-service priority register (ispr) 76543210 ispr ispr7 ispr6 ispr5 ispr4 ispr3 ispr2 ispr1 ispr0 address fffff1fah after reset 00h bit position bit name function 7 to 0 ispr7 to ispr0 indicates the priority of the interrupt that is being acknowledged. 0: interrupt request having priority n has not been acknowledged 1: interrupt request having priority n is being acknowledged remark n = 7 to 0 (priority levels)
chapter 8 intc preliminary user?s manual a13971ej7v0um 214 8.3.5 maskable interrupt status flag (id) this flag, which controls the operation status of maskable interrupts, stores information indicating whether the acknowledgement of interrupt requests is permitted or prohibited. it is assigned to bit 5 of the program status word (psw). figure 8-11. program status word (psw) 31 876543210 psw000000000000000000000000 np ep id sat cy ov sz after reset 00000020h bit position bit name function 5 id indicates whether maskable interrupt service is permitted or prohibited. 0: the acknowledgement of maskable interrupts is permitted 1: the acknowledgement of maskable interrupts is prohibited (pending) this bit is set (1) by the di instruction and cleared (0) by the ei instruction. its value is also rewritten by the reti instruction or the ldsr instruction for the psw. non-maskable interrupts and exceptions are acknowledged regardless of the status of this flag. also, when a maskable interrupt is acknowledged, the id flag is automatically set (1). an interrupt request that is generated while acknowledgement is prohibited (id = 1), is acknowledged when the pifn bit of the picn register is set (1) and the id flag is cleared (0).
chapter 8 intc preliminary user?s manual a13971ej7v0um 215 8.4 software exception a software exception, which is an exception that is generated when the cpu executes the trap instruction, can always be acknowledged. 8.4.1 operation if a software exception is generated, the cpu performs the following processing and shifts control to the handler routine. <1> save the restored pc in the eipc. <2> save the current psw in the eipsw. <3> write the exception code in the lower 16 bits (eicc) of the ecr (interrupt source). <4> set the ep and id bits of the psw. <5> set the handler address (00000040h or 00000050h) for the software exception in the pc and shift control. figure 8-12 shows the processing format of software exception processing. figure 8-12. software exception processing format eipc restored pc eipsw psw ecr.eicc exception code psw.ep 1 psw.id 1 pc handler address cpu processing trap instruction note exception processing note the trap instruction format is ?trap vector? (where vector is a value from 0 to 1fh). the handler address is determined by the trap instruction operand (vector). when vector is 0 to 0fh, the address is 00000040h. when vector is 10h to 1fh, the address is 00000050h.
chapter 8 intc preliminary user?s manual a13971ej7v0um 216 8.4.2 restore control is returned from software exception processing according to the reti instruction. when the reti instruction is executed, the cpu performs the following processing and shifts control to the restored pc address. <1> since the ep bit of the psw is 1, fetch the restored pc and psw from the eipc and eipsw. <2> shift control to the fetched restored pc address and psw status. figure 8-13 shows the processing format of the reti instruction. figure 8-13. reti instruction processing format 0 psw.ep pc eipc psw eipsw 1 0 1 pc fepc psw fepsw psw.np original processing restored reti instruction caution if the psw.ep bit and psw.np bit are changed by the ldsr instruction during software exception processing, then in order to restore the pc and psw correctly when control is returned according to the reti instruction, the ldsr instruction must be used to return psw.ep to 1 immediately before executing the reti instruction. remark the solid line indicates the cpu processing flow.
chapter 8 intc preliminary user?s manual a13971ej7v0um 217 8.5 exception trap the exception trap is an interrupt that is requested when the illegal execution of an instruction occurs. in the NB85E, the illegal opcode exception (ilgop: illegal opcode trap) is assigned for the exception trap. an illegal opcode exception is generated when the sub-opcode of the instruction to be executed next is an illegal opcode. 8.5.1 illegal opcode the illegal opcode, which has a 32-bit long instruction format, is defined as an arbitrary opcode in which bits 10 to 5 are 111111b, bits 26 to 23 are 0111b to 1111b, and bit 16 is 0b. figure 8-14. illegal opcode 15 11 10 54 031 0 1 1 1 1 1 1 1 to 0 27 26 23 22 16 11111 1 17 remark indicates an arbitrary value. caution since a new instruction may be assigned in the future for the illegal opcode, we recommend that this opcode not be used.
chapter 8 intc preliminary user?s manual a13971ej7v0um 218 8.5.2 operation if an exception trap is generated, the cpu performs the following processing and shifts control to the handler routine. <1> save the restored pc in the dbpc. <2> save the current psw in the dbpsw. <3> set the np, ep, and id bits of the psw. <4> set the handler address (00000060h) for the exception trap in the pc and shift control. figure 8-15 shows the processing format of exception trap processing. figure 8-15. exception trap processing format dbpc restored pc dbpsw psw psw.np 1 psw.ep 1 psw.id 1 pc 00000060h cpu processing exception processing exception trap (ilgop) is generated 8.5.3 restore control cannot return from an exception trap. perform a system reset according to dcresz input.
chapter 8 intc preliminary user?s manual a13971ej7v0um 219 8.6 interrupt response time except in the following cases, the interrupt response time is a minimum of 5 clocks. to input interrupt requests continuously, leave a space of at least 5 clocks between interrupt request inputs. ? during software or hardware stop mode ? when an external bus is accessed ? when there are two or more successive interrupt request non-sampling instructions (see 8.7 periods when interrupts cannot be acknowledged ). ? when the interrupt control register is accessed figure 8-16. example of pipeline operation when interrupt request is acknowledged (outline) vbclk (input) 5 system clocks interrupt request if id ex mem wb instruction 1 ifx idx int1 int2 int3 int4 if id ex instruction 2 interrupt acknowledgement operation instruction (first instruction of interru p t service routine ) remark int1 to int4: interrupt acknowledgement processing ifx: invalid instruction fetch idx: invalid instruction decode 8.7 periods when interrupts cannot be acknowledged an interrupt is acknowledged while an instruction is being executed. however, an interrupt is not acknowledged between an interrupt request non-sampling instruction and the subsequent instruction (the interrupt is held pending). the interrupt request non-sampling instructions are as follows. ? ei instruction ? di instruction ? ldsr reg2, 0x5 instruction (for psw) ? store instruction for specific area (xfff100h to xfff1ffh note , xfff900h to xfff9ffh) note the imr0 to imr3, pic0 to pic63, ispr, prcmd, and psc registers are allocated to a part of this area.
preliminary user?s manual a13971ej7v0um 220 chapter 9 test function the NB85E is equipped with an on-chip test interface control unit (tic) for testing the NB85E itself or connected peripheral macros via the test buses (tbi39 to tbi0 and tbo34 to tbo0). the test buses are effective when the test and bunri signals are active. 9.1 test pins 9.1.1 test bus pins (tbi39 to tbi0 and tbo34 to tbo0) the test bus pins are used in place of normal pins when the NB85E is in unit test mode. always extend these pins outside of the asic (they can be used in combination with normal pins). for details, refer to the various cell-based ic family design manuals. 9.1.2 bunri and test pins these pins are used to select normal, unit test, or standby test mode. table 9-1. list of test mode settings bunri pin input level test pin input level mode low level arbitrary normal mode high level low level standby test mode high level high level unit test mode (1) normal mode this is the mode the user normally uses. when a low level signal is being input to the bunri pin, the pins other than the test pins are enabled, and the NB85E is in normal mode. at this time, input to the tbi39 to tbi0 pins is ignored, and the tbo34 to tbo0 pins are set to high impedance. (2) unit test mode and standby test mode when a high-level signal is being input to the bunri pin, the NB85E is in test mode. the two types of test mode are unit test mode and standby test mode. circuits should be designed so that floating or bus contention does not occur for the pins constituting the bus (excluding test pins) during unit or standby test mode (for the pin status in each mode, see 2.4 pin status ). (a) unit test mode when a high-level signal is being input to the bunri and test pins, the input from the tbi39 to tbi0 pins is enabled in their place. also, the test result is output from the tbo34 to tbo0 pins. input/output signals from the following pins are also valid in test mode, and operate in the same way as in normal mode. accordingly, in test mode, be sure to handle these pins as indicated in 9.4 handling of each pin in test mode . ? vsb pins ? npb pins ? vfb pins
chapter 9 test function preliminary user?s manual a13971ej7v0um 221 ? vdb pins ? instruction cache pins ? data cache pins ? rcu pins caution unit test mode is used for tests performed by nec. the test patterns are provided by nec. (b) standby test mode when a high-level signal is being input to the bunri pin and a low-level signal is being input to the test pin, the NB85E is in standby test mode. the input to the tbi39 to tbi0 pins is ignored, and the tbo34 to tbo0 pins are set to high impedance. 9.2 list of test interface signals signal name i/o function phtdin1, phtdin0 output dedicated test signals output to peripheral macros phtdo1, phtdo0 input dedicated test signals input from peripheral macros tesen output enable signal output for setting peripheral macros to test mode vptclk output peripheral macro test clock output phtest output status signal output pin indicating peripheral test mode status tmode1 output test mode selection output tmode0 output these are nec reserved pins. leave them open. tbredz output caution the above signals are only required for tests performed at nec.
chapter 9 test function preliminary user?s manual a13971ej7v0um 222 9.3 example of connection of peripheral macro in test mode the npb peripheral macro, memc (NB85E500/nu85e500, nu85e502), instruction cache (NB85E212, NB85E213), and data cache (NB85E252, NB85E263) supported by nec are tested via the NB85E. an example of the connections between the NB85E, the npb peripheral macro, and the memc is shown below.
chapter 9 test function preliminary user?s manual a13971ej7v0um 223 figure 9-1. peripheral macro connection example NB85E vpresz vptclk phtdin0 phtdin1 phtdo0 note 1 phtdo1 note 2 phtest tmode0 tmode1 tbredz tbi39 tbi0 tbo34 tbo0 test bunri vpresz vptclk vptesin1 vptesin2 vptesof1 vptesof2 npb vpresz vptclk phtdin0 phtdin1 phtdo0 phtdo1 phtest vsb memc (nu85e502) vbclk vptclk vbclk vbclk vpresz tesen tesen tbi39 tbi0 tbo34 tbo0 test bunri vbclk open npb peripheral macro memc (NB85E500/nu85e500) npb test register note 3 open vsb notes 1. when more than one npb peripheral macro is connected, signals are input to the vptesof1 pin of each macro via an or circuit. 2. when more than one npb peripheral macro is connected, signals are input to the vptesof2 pin of each macro via an or circuit. 3. refer to the cb-9 family vx/vm type design manual NB85E, NB85Et .
chapter 9 test function preliminary user?s manual a13971ej7v0um 224 9.4 handling of each pin in test mode (1) pins other than those for test mode (a) i/o pins when the peripheral macro is tested via test interface pins, if the peripheral macro and user logic are both connected to vsb and npb, it may cause the signals to collide in test mode. in order to avoid signal collision, it is necessary to validate only the peripheral macro signals. because of this, make sure that the following i/o pins connected to user logic are designed on the user logic side to become high impedance in test mode (see figure 9-2 ). note that this does not apply to cases where each signal has been pre-designed not to collide in test mode. ? vbwait ? vblast ? vbahld ? vbseq2 to vbseq0 ? vbbstr ? vdcsz7 to vdcsz0 ? vdselpz ? vbttyp1, vbttyp0 ? vbsize1, vbsize0 ? vbbenz3 to vbbenz0 ? vbwrite ? vblock ? vbctyp2 to vbctyp0 ? vba27 to vba0 ? vbstz ? vpd15 to vpd0 ? vbd31 to vbd0 special handling is not required for i/o pins other than those above (handle as in normal mode). caution the test bus automatic connection tool provided by nec does not support the NB85E. test bus connection must therefore be performed on the user side.
chapter 9 test function preliminary user?s manual a13971ej7v0um 225 figure 9-2. user logic design example user logic bunri v s b peripheral macro user logic n p b bbr tic NB85E bunri peripheral macro asic (b) input pins input a low level to the vareq pin. special handling is not required for pins other than the vareq pin (handle as in normal mode). (c) output pins special handling is not required (handle as in normal mode).
chapter 9 test function preliminary user?s manual a13971ej7v0um 226 (2) test mode pins handle the pins for test mode as indicated below. pin name i/o connection method when npb peripheral is connected when memc is connected when cache is connected when neither npb peripheral, memc, nor cache is connected phtdon input connect to the vptesofn pin. connect to the phtdon pin of the NB85E500/nu85e500. ? input low level. phtdinn output connect to the vptesinn pin. connect to the phtdinn pin of the NB85E500/nu85e500. ? leave open. vpresz output connect to the npb test register. connect to the vpresz pin of the NB85E500/nu85e500. connect to the vpresz pin. vptclk output connect to the vptclk pin. connect to the vptclk pin of the NB85E500/nu85e500, nu85e502. connect to the vptclk pin. tesen output leave open. ? ? phtest output connect to the npb test register. connect to the phtest pin of the NB85E500/nu85e500. ? tmoden, tbredz output leave open. remark n = 1, 0 (3) precautions when NB85E901 is connected when the NB85E901 (rcu) is connected to the NB85E, the following pins are used in the single-unit test mode. all of these pins should be attached off chip as external pins. ? tbi39 to tbi0 note 1 ? drstz note 2 ? tbo34 to tbo0 note 1 ? dms note 2 ? test note 1 ? ddi note 2 ? bunri ? ddo note 2 ? dck note 2 ? dbint notes 1, 2 notes 1. can be used as an alternate function pin with a pin used in normal mode. 2. pins of the NB85E901 (for details, refer to chapter 10 NB85E901 .)
preliminary user?s manual a13971ej7v0um 227 chapter 10 NB85E901 (under development) 10.1 overview the NB85E901 (rcu: run control unit) is a run control unit that realizes the execution of jtag communication and debug processing. connection of the NB85E901 with an n-wire type in-circuit emulator (n-wire type ie) makes it possible to perform on-chip debugging on the NB85E. 10.1.1 symbol diagram out in out in in in/out in dbint resetz stopz nmi (2:0) vareq dms ddi ddo drstz dck in in in in out in in in vbclk dbi (5:0) dbo (14:0) dbb (15:0) tmode1 vbwait dcresz dcstopz bunri in test in in in out romtype dcop (13:0) out in dcnmi (2:0) dcvareq vbtclk dcwaitz stpak out out in out in waitz in
chapter 10 NB85E901 preliminary user?s manual a13971ej7v0um 228 10.2 pin functions 10.2.1 pin function list pin name i/o function dck input clock input for rcu drstz input reset input for rcu dms input debug mode selection input ddi input debug data input ddo output debug data output n-wire type ie connection pins dbint input external debug interrupt input resetz input system reset input stopz input hardware stop mode request input nmi2 to nmi0 input non-maskable interrupt input vareq input bus access right request input waitz input wait request input romtype input nec reserved pin (input low level) system control pins dcop13 to dcop0 output nec reserved pin (leave open) vbclk input system clock input dbi5 to dbi0 output debug control output dbo14 to dbo0 input debug control input dbb15 to dbb0 i/o debug control i/o tmode1 input test mode selection input vbwait input wait response input dcresz output reset output dcstopz output hardware stop mode request output dcnmi2 to dcnmi0 output non-maskable interrupt output dcvareq output bus access right request output NB85E connection pins vbtclk input clock input for testing dcwaitz output wait request output peripheral connection pins stpak input stop mode request acknowledge input bunri input normal/test mode selection input test mode pins test input test bus control input
chapter 10 NB85E901 preliminary user?s manual a13971ej7v0um 229 10.2.2 pin functions (1) n-wire type ie connection pins caution n-wire type ie connection pins (dck, drstz, dms, ddi, ddo, dbint) must be attached off the chip as external pins since they are used in the single-unit test mode. do not use these pins as alternate function pins (however, the dbint pin can be used as the alternate function of a pin other than the tbi39 to tbi0, tbo34 to tbo0, test, bunri, dck, drstz, dms, ddi, and ddo pins). (a) dck (input) this is the pin to which the clock for the rcu is input from the n-wire type ie. (b) drstz (input) this is the rcu reset input pin. the rcu is reset asynchronously when a low level is input. (c) dms (input) this is the pin to which the debug mode selection is input from the n-wire type ie. (d) ddi (input) this is the pin to which the debug data is input from the n-wire type ie. (e) ddo (output) this is the pin from which the debug data is output to the n-wire type ie. (f) dbint (input) this is the external debug interrupt input pin. an active level (high level) is input when shifting to the debug mode by an external request. (2) system control pins (a) resetz (input) this is the system reset input pin. (b) stopz (input) this is the hardware stop mode request input pin. (c) nmi2 to nmi0 (input) these are non-maskable interrupt input pins. (d) vareq (input) this is the bus access right request input pin. (e) waitz (input) this is the external wait request input pin.
chapter 10 NB85E901 preliminary user?s manual a13971ej7v0um 230 (f) romtype (input) this is an nec reserved pin. always input a low level. (g) dcop13 to dcop0 (output) these are nec reserved pins. leave them open. (3) NB85E connection pins (a) vbclk (input) this is the system clock input pin. (b) dbi5 to dbi0 (output) these are debug control output pins. connect them to pins dbi5 to dbi0 on the NB85E. (c) dbo14 to dbo0 (input) these are debug control input pins. connect them to pins dbo14 to dbo0 on the NB85E. (d) dbb15 to dbb0 (i/o) these are debug control i/o pins. connect them to pins dbb15 to dbb0 on the NB85E. (e) tmode1 (input) this is the test mode selection input pin. connect it to the tmode1 pin on the NB85E. (f) vbwait (input) this is the wait response input pin. (g) dcresz (output) this is the reset output pin. connect it to the dcresz pin on the NB85E. (h) dcstopz (output) this is the hardware stop mode request output pin. connect it to the dcstopz pin on the NB85E. (i) dcnmi2 to dcnmi0 (output) these are non-maskable interrupt output pins. connect them to pins dcnmi2 to dcnmi0 on the NB85E. (j) dcvareq (output) this is the bus access right request output pin. connect it to the vareq pin on the NB85E. (k) vbtclk (input) this is the test clock input pin. connect it to the vptclk pin on the NB85E.
chapter 10 NB85E901 preliminary user?s manual a13971ej7v0um 231 (4) peripheral connection pins (a) dcwaitz (output) this is the external wait request output pin. (b) stpak (input) this is the stop mode request acknowledge input pin. input the stpak signal from the memory controller. (5) test mode pins (a) bunri (input) this is the input pin for selecting normal mode or test mode. (b) test (input) this is the test bus control input pin.
chapter 10 NB85E901 preliminary user?s manual a13971ej7v0um 232 10.2.3 recommended connection of unused pins pin name i/o recommended connection method n-wire type ie connection pins dck, drstz, dms, ddi input ? ddo output ? dbint input input a low level. system control pins resetz input ? stopz, waitz input input a high level. nmi2 to nmi0, vareq, romtype input input a low level. dcop13 to dcop0 output leave open. NB85E connection pins vbclk, dbo14 to dbo0, tmode1, vbtclk input ? dbi5 to dbi0 output ? dbb15 to dbb0 i/o ? vbwait input input a low level. dcresz, dcstopz, dcnmi2 to dcnmi0, dcvareq output leave open. peripheral connection pins dcwaitz output leave open. stpak input input the stprq signal of the NB85E. test mode pins bunri, test input ?
chapter 10 NB85E901 preliminary user?s manual a13971ej7v0um 233 10.2.4 pin status the following table shows the status in each operating mode of the pins that have output functions. table 10-1. pin status in each operating mode pin status pin name reset note software stop mode hardware stop mode halt mode standby test mode unit test mode ddo l/ operates l/ operates l/ operates l/ operates l/ operates l/ operates dcop13 to dcop10 l/ operates l/ operates l/ operates l/ operates l/ operates l/ operates dcop9 l/l l/ operates l/ operates l/ operates l/ operates l/ operates dcop8 to dcop3 l/ operates l/ operates l/ operates l/ operates l/ operates l/ operates dcop2 h/ operates h/ operates h/ operates h/ operates h/ operates h/ operates dcop1, dcop0 l/ operates l/ operates l/ operates l/ operates l/ operates l/ operates dbi5 h/ operates h/ operates h/ operates h/ operates h/ operates h/ operates dbi4 to dbi2 l/ operates l/ operates l/ operates l/ operates l/ operates l/ operates dbi1 h/ operates h/ operates h/ operates h/ operates h/ operates h/ operates dbi0 l/h l/h l/h l/h l/h l/h db15 to dbb0 retained/ retained retained/ retained retained/ retained retained/ retained retained/ retained retained/ operates dcresz resetz resetz resetz resetz resetz undefined dcstopz stopz stopz stopz stopz stopz undefined dcnmi2 to dcnmi0 nmi2 to nmi0 nmi2 to nmi0 nmi2 to nmi0 nmi2 to nmi0 nmi2 to nmi0 undefined dcvareq vareq vareq vareq vareq vareq undefined dcwaitz waitz waitz waitz waitz waitz undefined note when a low level is input to the dcresz pin and an external clock is input to the vbclk pin. remarks 1. l: low-level output h: high-level output retained: retains previous status 2. the item to the left of the slash (/) indicates the status when a low level is input to the drstz pin, and the item to right indicates the status when a high level is input to the drstz pin. 3. the status of the dcresz, dcstopz, dcnmi2 to dcnmi0, dcvareq, and dcwaitz pins indicates the status either when a low level is input to the drstz pin or when a high level is input to the drstz pin and the external input signals (resetz, stopz, nmi2 to nmi0, vareq, and waitz) have not been masked.
chapter 10 NB85E901 preliminary user?s manual a13971ej7v0um 234 caution the following input pins must be set according to the table below in the respective operating modes. pin status pin name reset note software stop mode hardware stop mode halt mode standby test mode unit test mode drstz l/h l/h l/h l/h l/h l/h ddi h/ operates h/ operates h/ operates h/ operates h/ operates h/ operates dbint l/ operates l/ operates l/ operates l/ operates l/ operates l/ operates romtypellllll note when a low level is input to the dcresz pin and an external clock is input to the vbclk pin. remarks 1. l: low-level output h: high-level output retained: retains previous status 2. the item to the left of the slash (/) indicates the status when a low level is input to the drstz pin, and the item to right indicates the status when a high level is input to the drstz pin.
chapter 10 NB85E901 preliminary user?s manual a13971ej7v0um 235 10.3 debug function (1) debug interface communication with the host machine is performed via the n-wire type ie using the dck, drstz, dms, ddi, and ddo signals. jtag communication specification is used for the interface. the boundary scan function is not supported. (2) on-chip debug by connecting with the n-wire type ie, it is possible to debug the NB85E901 on the NB85E chip. for details on the above connection, refer to 10.5 n-wire type ie connection . (3) forcible reset function the NB85E901 unit can be forcibly reset. (4) break reset function the cpu can be started in debug mode immediately after cpu reset release. (5) forcible break function execution of the user program can be forcibly interrupted. note that the illegal opcode exception handler (start address: 00000060h) cannot be used. (6) debug interrupt interface the forcible break function can be executed by inputting a high level to the dbint pin. remark it is also possible to release the halt, software stop, and hardware stop modes by dbint input. (7) breakpoint function execution of the user program can be interrupted at an arbitrary address. also, data access to an arbitrary address can be interrupted. note that the illegal opcode exception handler (start address: 00000060h) cannot be used. there are two kinds of instruction/access alternate breakpoints: a pre-execution break and a post-access execution break. (8) debug monitor function a debug-dedicated memory space, which is different to the user memory space, is used during debugging (background monitor format). execution of the user program can be started from an arbitrary address. it is also possible to read/write the user resource (such as memory and i/o) and download the user program during a user program interruption. (9) mask function the external input signals (resetz, stopz, nmi2 to nmi0, vareq, waitz) can be masked.
chapter 10 NB85E901 preliminary user?s manual a13971ej7v0um 236 10.4 NB85E connection example figure 10-1 shows an example of the connection between the NB85E901 and the NB85E. figure 10-1. NB85E901 and NB85E connection example NB85E vbclk dck NB85E901 (rcu) dbi5 to dbi0 dbo14 to dbo0 dbb15 to dbb0 dcresz dcstopz dcnmi1 vbclk dbi5 to dbi0 dbo14 to dbo0 dbb15 to dbb0 dcresz note 1 dcstopz note 2 dcnmi1 note 3 clock generator (cg) vbclk dcvareq NB85E500/ nu85e500 (memc) vareq note 4 drstz dms ddi ddo dbint bunri test connection with n-wire type in-circuit emulator vptclk dcnmi2 dcnmi2 note 3 dcnmi0 dcnmi0 note 3 tmode1 tmode1 vbwait vbwait resetz stopz nmi2 nmi1 nmi0 dcresz dcstopz dcnmi1 dcnmi2 dcnmi0 bunri test dcwaitz note 6 vareq note 6 waitz note 5 vareq waitz romtype dcop13 ? dcop0 ? waitz stpak stpak vbtclk vbwait stpak note 6 l open notes 1. input the signal input from the resetz pin of the rcu and output from the dcresz pin. 2. input the signal input from the stopz pin of the rcu and output from the dcstopz pin. 3. input the signal input from the nmin pin of the rcu and output from the dcnmin pin (n = 2 to 0). 4. input the signal input from the vareq pin of the rcu and output from the dcvareq pin. 5. input the signal input from the waitz pin of the rcu and output from the dcwaitz pin. 6. if the memc is not used, process the pin as shown in 10.2.3 recommended connection of unused pins.
chapter 10 NB85E901 preliminary user?s manual a13971ej7v0um 237 10.5 n-wire type ie connection in order to connect the n-wire type ie (ie-70000-mc-nw-a), it is necessary to mount a connector for ie connection and a connection circuit on the target system. figure 10-2. n-wire type ie connection to host machine target system ie-70000-mc-nw-a connector for ie connection (8830e-026-170s/l) (product of kel corporation) 10.5.1 ie connector (target system side) figure 10-3 shows the pin layout of the ie connector (target system side), and table 10-1 describes the pin functions. remark the recommended connectors are as follows. ? 8830e-026-170s (product of kel corporation): 26-pin straight type ? 8830e-026-170l (product of kel corporation): 26-pin right angle type figure 10-3. ie connector pin layout diagram (target system side) a13 a12 a11 a3 a1 a2 b1 b2 b3 b13 b11 b12 (top view)
chapter 10 NB85E901 preliminary user?s manual a13971ej7v0um 238 table 10-2. ie connector pin functions (target system side) pin no. pin name i/o pin function a1 trcclk input trace clock input a2 trcdata0 input trace data 0 input a3 trcdata1 input trace data 1 input a4 trcdata2 input trace data 2 input a5 trcdata3 input trace data 3 input a6 trcend input trace data end input a7 ddi output debug serial interface data output a8 dck output debug serial interface clock output a9 dms output debug serial interface transfer mode selection output a10 ddo input debug serial interface data input a11 drstz output dcu reset output a12 (reserved) ? (leave open) a13 (reserved) ? (leave open) b1 gnd ? ? b2 gnd ? ? b3 gnd ? ? b4 gnd ? ? b5 gnd ? ? b6 gnd ? ? b7 gnd ? ? b8 gnd ? ? b9 gnd ? ? b10 gnd ? ? b11 (reserved) ? (leave open) b12 (reserved) ? (leave open) b13 v dd ? +3.3 v input (for monitoring target power supply application)
chapter 10 NB85E901 preliminary user?s manual a13971ej7v0um 239 10.5.2 example of recommended circuit when connecting NB85E901 and NB85E figure 10-4 shows an example of the circuit recommended for ie connector section (target system side). figure 10-4. example of recommended circuit for ie connection (NB85E + NB85E901) trcdata0 trcdata1 trcdata2 trcdata3 trcend trcclk a1 a2 a3 a4 a5 a6 dck dms ddi ddo drstz dbint dck dms ddi ddo drstz note 1 a8 note 2 a9 note 2 a7 note 2 a10 a11 4.7 k ? +3.3 v note 3 22 ? 50 k ? external event detection device, etc. NB85E+NB85E901 ie connector (target system side) 8830e-026-170s/l v dd +3.3 v b13 gnd b1 to b10 a12 a13 b11 b12 (open) (open) (open) (open) (reserved) (reserved) (reserved) (reserved) 3 v buffer note 4 asic notes 1. make the clock pattern length as short as possible, and shield it by surrounding it with gnd. avoid exceeding a pattern length of 100 mm. 2. make the pattern length as short as possible. avoid exceeding a pattern length of 100 mm. 3. recommended buffer: sn74lvc541a (product of ti corporation) or tc74lcx541f (product of toshiba corporation) 4. an output buffer with a drive capability of at least 6 ma is recommended. remarks 1. the v dd pin (pin b13) of the ie connector (target system side) is only used to detect whether power has been applied to the target system. 2. the dbint pin is optional. however, because the dbint pin is necessary for testing, it must be output off the chip as an external pin, even when not being used (the dbint pin can be used as the alternate function of a pin other than the test bus pins (tbi39 to tbi0, tbo34 to tbo0)). when it is unnecessary to input a debug interrupt externally, input a low level to this pin.
preliminary user?s manual a13971ej7v0um 240 appendix a rom/ram access timing figure a-1. rom access timing vbclk (input) iromen (output) iroma19 to iroma2 (output) iromz31 to iromz0 (input) a0 a1 hold a3 d0 d1 a2 a4 d2 note d3 a5 d4 note data should be retained from when the iromen output becomes high level until the vbclk signal rises. remarks 1. ax: arbitrary address dx: data corresponding to address ?ax? 2. { : rom data sampling timing
appendix a rom/ram access timing preliminary user?s manual a13971ej7vum 241 figure a-2. ram access timing (a) read timing vbclk (input) iramrwb (output) irama27 to irama2 (output) iramz31 to iramz0 (input) iramen (output) a0 a1 a2 d0 d1 d2 remarks 1. ax: arbitrary address dx: data corresponding to address ?ax? 2. { : ram data sampling timing (b) write timing vbclk (input) iramrwb (output) irama27 to irama2 (output) iramwr3 to iramwr0 (output) iramen (output) iraoz31 to iraoz0 (output) d0 d1 d2 a0 a1 a2 we0 we1 we2 remark ax: arbitrary address dx: data corresponding to address ?ax?
preliminary user?s manual a13971ej7v0um 242 appendix b index [a] address space .........................................................55 application system example ....................................18 [b] bbr ........................................................................114 bc15 to bc0 ..........................................................149 bcu..........................................................................71 bcunch ..................................................................36 bcu-related register setting examples .................88 bec ..........................................................................84 ben0.........................................................................84 bhc..........................................................................87 bhn0 ........................................................................87 bhn1 ........................................................................87 block transfer mode ...............................................163 bpc ..........................................................................82 bsc ..........................................................................83 bsn1, bsn0..............................................................83 bunri ......................................................................42 bus master transition..............................................108 bus size configuration register ..............................83 bus size setting function ........................................83 [c] cache configuration.................................................87 cache configuration register ..................................87 cgrel .....................................................................33 ch3 to ch0 ............................................................153 chip area select control register 0 ........................74 chip area select control register 1 ........................75 clock control..........................................................137 command register..................................................132 cpu..........................................................................48 csc0........................................................................74 csc1........................................................................75 csn3 to csn0 ..........................................................74 ctbp ........................................................................52 ctpc........................................................................52 ctpsw ....................................................................52 cy ............................................................................54 [d] da15 to da0 .......................................................... 148 da27 to da16 ........................................................ 147 dad1, dad0.......................................................... 151 dadc0 to dadc3.................................................. 150 data area ................................................................. 57 data transfer using vsb......................................... 91 dbb15 to dbb0 ....................................................... 38 dbc0 to dbc3....................................................... 149 dbi5 to dbi0 ............................................................ 38 dbo14 to dbo0 ...................................................... 38 dbpc ....................................................................... 52 dbpsw.................................................................... 52 dchc0 to dchc3 ................................................. 152 dcnmi2 to dcnmi0................................................. 34 dcresz .................................................................. 32 dcstopz................................................................ 33 dda0 to dda3....................................................... 147 ddis ...................................................................... 153 debug function ..................................................... 235 dma addressing control registers 0 to 3................ 150 dma bus state ...................................................... 155 dma channel control registers 0 to 3..................... 152 dma channel priorities.......................................... 144 dma destination address registers 0 to 3 .............. 147 dma disable status register ................................... 153 dma restart register............................................... 153 dma source address registers 0 to 3..................... 145 dma transfer count registers 0 to 3 ....................... 149 dma transfer start factors ................................... 165 dma transfer timing examples ............................ 170 dmac .................................................................... 142 dmac bus cycle state transitions .......................... 157 dmactv3 to dmactv0 .......................................... 34 dmarq3 to dmarq0 ............................................. 33 dmtco3 to dmtco0 .............................................. 33 drst ..................................................................... 153 ds1, ds0 ............................................................... 150 dsa0 to dsa3 ....................................................... 145
appendix b index preliminary user?s manual a13971ej7v0um 243 [e] ecr.......................................................................... 52 eicc......................................................................... 53 eipc......................................................................... 52 eipsw ..................................................................... 52 en3 to en0 ............................................................ 153 endian configuration register ................................. 84 endian setting function ........................................... 84 enn ........................................................................ 152 ep ............................................................................ 54 evad15 to evad0................................................... 39 evastb ................................................................... 38 evclrip.................................................................. 39 evdstb ................................................................... 38 evien ...................................................................... 39 evintak .................................................................. 39 evintlv6 to evintlv0 .......................................... 39 evintrq ................................................................. 39 evirel .................................................................... 39 evlkrt ................................................................... 39 evoen..................................................................... 39 example of connection of peripheral macro in test mode ...................................................................... 222 external memory ...................................................... 18 external memory area .............................................. 64 [f] fcomb .................................................................... 41 fecc ....................................................................... 53 fepc........................................................................ 52 fepsw .................................................................... 52 flyby transfer ......................................................... 165 [g] general-purpose registers ....................................... 50 [h] halt mode ............................................................ 133 handling of each pin in test mode ........................ 224 hardware stop mode ........................................... 136 hwstoprq ............................................................ 33 [i] ibaack.................................................................... 35 ibbtft .................................................................... 36 ibdle3 to ibdle0 ................................................... 35 ibdrdy ................................................................... 35 ibdrrq................................................................... 35 ibea25 to ibea2 ..................................................... 35 ibedi31 to ibedi0 ................................................... 35 id ............................................................................. 54 idaack ................................................................... 36 iddarq................................................................... 36 iddrdy ................................................................... 38 iddrrq................................................................... 37 iddwrq.................................................................. 37 idea27 to idea0 ..................................................... 38 ided31 to ided0..................................................... 38 ides ........................................................................ 38 idhum ..................................................................... 38 idmastp................................................................. 33 idretr ................................................................... 37 idrrdy ................................................................... 37 idseq2.................................................................... 37 idseq4.................................................................... 37 idunch................................................................... 37 ifid256.................................................................... 40 ifimaen .................................................................. 40 ifimode3, ifimode2 ............................................. 41 ifinsz1, ifinsz0 .................................................... 41 ifira64, ifira32, ifira16 ..................................... 40 ifirabe................................................................... 41 ifirase................................................................... 41 ifirob2................................................................... 40 ifirobe .................................................................. 41 ifirome.................................................................. 39 ifiropr .................................................................. 41 ifiunch0 ................................................................ 41 ifiunch1 ................................................................ 41 ifiuswe.................................................................. 41 ifiwrth.................................................................. 41 iiaack ..................................................................... 36 iibtft...................................................................... 36 iidlef ..................................................................... 36 iidrrq .................................................................... 36 iiea25 to iiea2 ........................................................ 36 iiedi31 to iiedi0...................................................... 36 iircan..................................................................... 36 illegal opcode ........................................................ 217
appendix b index preliminary user?s manual a13971ej7v0um 244 imr0 to imr3 .........................................................212 initn.......................................................................152 in-service priority register .......................................213 int63 to int0 ...........................................................34 intc .......................................................................196 internal block diagram ..............................................22 interrupt control registers 0 to 63 ...........................211 interrupt mask registers 0 to 3................................212 interrupt response time........................................219 interrupt/exception list...........................196, 197, 198 interrupt/exception table...........................................59 intm.......................................................................130 ir....................................................................145, 147 irama27 to irama2 ................................................34 iramen....................................................................35 iramrwb ................................................................35 iramwr3 to iramwr0 ..........................................35 iramwt...................................................................35 iramz31 to iramz0 ................................................34 iraoz31 to iraoz0.................................................34 iroma19 to iroma2 ...............................................34 iromae ...................................................................34 iromcs ...................................................................34 iromen ...................................................................34 iromia.....................................................................34 iromwt ..................................................................34 iromz31 to iromz0................................................34 irrsa ......................................................................37 ispr .......................................................................213 ispr7 to ispr0......................................................213 [l] line transfer mode .................................................161 [m] maskable interrupt priorities ...................................207 maskable interrupts................................................204 memory banks..........................................................71 misalign access timing ...........................................112 mlen ......................................................................152 [n] NB85E901 ..............................................................227 NB85E901 and NB85E connection example.........236 NB85E901 (rcu) interface ......................................70 next address setting function .............................. 154 nmi ........................................................................ 199 nmi0m ................................................................... 130 nmi1m ................................................................... 130 nmi2m ................................................................... 130 non-maskable interrupts........................................ 199 normal mode ......................................................... 220 np ............................................................................ 54 npb.......................................................................... 17 npb read/write timing......................................... 122 npb strobe wait control register......................... 119 n-wire type ie connection ................................... 237 [o] on-chip debugging .................................................. 70 ov............................................................................ 54 [p] pa13 to pa00 .......................................................... 82 pa15 ........................................................................ 82 pc ............................................................................ 50 periods when interrupts cannot be acknowledged ........................................................................... 219 peripheral i/o area................................................... 62 peripheral i/o area select control register ............ 82 peripheral i/o registers........................................... 64 pheva..................................................................... 41 phtdin1, phtdin0 ................................................ 42 phtdo1, phtdo0 .................................................. 42 phtest................................................................... 42 pic0 to pic63 ........................................................ 211 pifn ....................................................................... 211 pin functions ..................................................... 24 pin status ................................................................ 45 pmkn ..................................................................... 211 power save control register ................................... 130 power save function............................................. 129 pprn2 to pprn0 ................................................... 211 prcmd.................................................................. 132 program area ........................................................... 56 program counter ...................................................... 51 program registers .................................................... 50 programmable chip select function ....................... 74 programmable peripheral i/o area........................ 116 programmable peripheral i/o area selection function ............................................................................. 80
appendix b index preliminary user?s manual a13971ej7v0um 245 psc........................................................................ 130 psw ......................................................................... 52 [r] r0 to r31.................................................................... 50 ram ......................................................................... 18 ram area ................................................................. 61 recommended connection of unused pins ............ 43 reg7 to reg0....................................................... 132 retry function........................................................ 121 rom......................................................................... 18 rom area................................................................. 59 rom relocation function........................................... 59 rom/ram access timing ................................. 240 [s] s ............................................................................. 54 sa15 to sa0........................................................... 146 sa27 to sa16......................................................... 145 sad1, sad0 .......................................................... 150 sat .......................................................................... 54 single transfer mode .............................................. 158 single-step transfer mode ...................................... 160 software exception ................................................ 215 software stop mode ............................................ 134 standby test mode ................................................. 221 stbc...................................................................... 129 stgn...................................................................... 152 stp ........................................................................ 130 stpak ..................................................................... 33 stprq ..................................................................... 33 suwl2 to suwl0 ................................................. 119 swstoprq ............................................................ 33 symbol diagram....................................................... 21 system registers ...................................................... 52 [t] tbi39 to tbi0 ........................................................... 42 tbo34 to tbo0........................................................ 42 tbredz ................................................................... 42 tcn ........................................................................ 152 tdir....................................................................... 151 tesen ..................................................................... 42 test ........................................................................ 42 test function................................................... 220 tm1, tm0............................................................... 151 tmode0.................................................................. 42 tmode1.................................................................. 42 transfer objects .................................................... 144 ttyp...................................................................... 151 two-cycle transfer ................................................. 165 [u] unit test mode ....................................................... 220 [v] vaack..................................................................... 28 vareq .................................................................... 28 vba27 to vba0 ....................................................... 29 vbahld .................................................................. 32 vbbenz3 to vbbenz0 ........................................... 29 vbbstr .................................................................. 31 vbclk ..................................................................... 33 vbctyp2 to vbctyp0 ........................................... 30 vbd31 to vbd0 ....................................................... 29 vbdc....................................................................... 32 vblast ................................................................... 31 vblock .................................................................. 30 vbseq2 to vbseq0 ............................................... 30 vbsize1, vbsize0 ................................................. 29 vbstz ..................................................................... 29 vbttyp1, vbttyp0 ............................................... 29 vbwait................................................................... 31 vbwrite ................................................................ 30 vdb ......................................................................... 18 vdcsz7 to vdcsz0 ............................................... 32 vdselpz ................................................................ 32 vfb.......................................................................... 18 vpa13 to vpa0 ....................................................... 28 vpd15 to vpd0 ....................................................... 28 vpdact .................................................................. 28 vplock .................................................................. 28 vpresz .................................................................. 42 vpretr .................................................................. 28 vpstb ..................................................................... 28 vptclk................................................................... 42 vpubenz................................................................ 28 vpwrite ................................................................ 28 vsb ......................................................................... 17 vswc.................................................................... 119 vswl2 to vswl0 ................................................. 120
appendix b index preliminary user?s manual a13971ej7v0um 246 [w] wait insertion function ..........................................119 [z] z ............................................................................ 54
preliminary user?s manual a13971ej7v0um 247 appendix c revision history a history of the revisions up to this edition is shown below. ?pages? indicates the pages of the earlier edition to which the revision was applied. (1) from 1st to 2nd pages description throughout internal rom, internal ram referred to as ?rom?, ?ram? respectively. p.28 modification of explanation of tesen, phtest pin functions in 2.1 list of pin functions p.29 addition of explanation 2.2.1 (3) vpwrite p.34 addition of explanation 2.2.4 (3) dmtco3 to dmtco0 p.39 modification of explanation of 2.2.12 (1) ifirome p.42 modification of explanations of 2.2.13 (6) tesen, (7) vptclk, (10) phtest pp.43, 44 modification of recommended connection of vblast, vbahld, idea27 to idea0, ifirob2, ifiwrth, ifiunch1, ifiunch0 in 2.3 handling of unused pins p.46 change of status of swstoprq, hwstoprq, stprq after reset in table 2-10 pin status in each operating mode p.58 modification of contents of note 2 in figure 3-8 data area (256 mb mode) p.67 modification of manipulatable bits of instruction cache control register (icc) in 3.5 (3) instruction cache control register pp.80, 82 addition of caution to 4.4 programmable peripheral i/o area selection function p.86 addition of caution to 4.7 cache configuration pp.87, 88 modification of figure 4-12 bpc, bsc, bec, bhc register setting example p.92 modification of table 4-6 vbwait, vbahld, and vblast signals pp.94 to 105 modification of remark in figure 4-14 read/write timing of bus slave connected to vsb p.108 modification of figure 5-2 NB85E and peripheral macro connection example p.121 modification of explanation in 6.2.1 power save control register (psc) p.127 modification of figure 6-5 software stop mode set/cancel timing example pp.128, 129 modification of figure 6-6 hardware stop mode set/cancel timing example p.133 modification of table 7-2 relationships between wait function and transfer object p.147 modification of figure 7-12 single transfer example 1 p.150 addition of 7.8.5 one-time transfer when executing single transfers using dmarqn signal p.154 addition of 7.14 (5) dma transfer end interrupt p.179 modification of explanation in 9.1.2 bunri and test pins p.180 modification of explanation of vptclk, phtest pin functions in 9.2 list of test interface signals p.181 modification of 9.3 example of connection of peripheral macro in test mode pp.182 to 184 modification of 9.4 handling of each pin in test mode
appendix c revision history preliminary user?s manual a13971ej7v0um 248 (2) from 2nd to 3rd (1/2) pages description pp.28, 29 change of ibbtft and ides pins to nec reserved pins pp.29, 30, 41, 45 modification of description of dbb15 to dbb0 and tmode1 pins p.33 addition of note to table 2-4 vbctyp2 to vbctyp0 signals p.35 addition of caution to 2.2.3 (1) dcresz p.35 addition of note to figure 2-1 acknowledgement of dcresz signal p.35 modification of description in 2.2.3 (3) cgrel p.36 deletion of part of description in 2.2.3 (7) stprq p.36 modification of description in 2.2.4 (1) idmastp p.36 modification of description in 2.2.4 (4) dmactv3 to dmactv0 p.36 deletion of part of description in 2.2.5 (2) int63 to int0 p.37 modification of description in 2.2.7 (5) iramwr3 to iramwr0 pp.38, 39 modification of description in 2.2.8 instruction cache pins pp.39 to 41 modification of description in 2.2.9 data cache pins p.45 modification of description in 2.2.13 (6) tesen p.45 addition of caution to 2.2.13 (9) vpresz p.46 modification of recommended connection method for stpak pin in 2.3 recommended connection of unused pins pp.48 to 50 modification of pin status of the following pins in unit test mode in table 2-10 pin status in each operating mode : npb pins, vsb pins, vfb pins, vdb pins, instruction cache pins, and data cache pins p.63 addition of caution to 3.4.2 ram area p.63 modification of address in figure 3-10 (d) when 60 kbytes is selected p.64 modification of caution in 3.4.3 peripheral i/o area p.65 addition of description to 3.5 peripheral i/o registers p.70 modification of 3.5.3 instruction cache control registers p.70 addition of 3.5.4 data cache control registers p.71 modification of 3.6.2 on-chip debugging pp.73 to 92 change of description ?block n? from previous edition to ?csn area? p.83 modification of figure 4-5 peripheral i/o area and programmable peripheral i/o area p.84 modification of caution 4 in 4.4 programmable peripheral i/o area selection function pp.87, 88 addition of 4.6.1 usage restrictions concerning big endian format with nec development tools p.94 addition of note to table 4-2 vbctyp2 to vbctyp0 signals pp.96 to 108 modification of diagrams of read/write timing when bus slave is connected to vsb in 4.9.3 read/write timing p.109 modification of figure 4-15 reset timing pp.110 to 113 addition of 4.9.5 bus master transition
appendix c revision history preliminary user?s manual a13971ej7v0um 249 (2/2) pages description p.116 modification of figure 5-2 NB85E and peripheral macro connection example p.117 modification of figure 5-3 peripheral i/o area and programmable peripheral i/o area p.121 modification of figure 5-6 npb strobe wait control register (vswc) p.121 addition of description and table to 5.2 wait insertion function pp.123 to 129 modification of 5.4 npb read/write timing pp.132, 133 modification of description in 6.2.1 power save control register (psc) p.132 addition of note to figure 6-2 power save control register (psc) p.135 addition of description in 6.3 (1) setting and operation status p.135 addition of caution to 6.3 (2) (b) cancellation by dcresz signal input p.136 addition of caution to 6.4 (2) (b) cancellation by dcresz signal input p.137 addition of caution to 6.5 (2) (b) cancellation by dcresz signal input pp.138, 139 modification of 6.6 (1) (b) when canceling software stop mode pp.140, 141 modification of 6.6 (2) (b) when canceling hardware stop mode p.143 modification of 7.1 features p.150 addition of description in 7.5.3 dma transfer count registers 0 to 3 (dbc0 to dbc3) p.158 deletion of description from 7.7.2 dmac bus cycle state transitions p.163 modification of 7.8.5 one-time transfer when executing single transfers using dmarqn signal p.164 modification of 7.9.1 two-cycle transfer p.164 deletion of part of description in 7.10 (1) request by external pin (dmarqn) p.165 modification of 7.11 output when dma transfer is complete p.166 modification of description and diagram and addition of caution in 7.12 forcible interruption p.167 addition of description and caution in 7.13 forcible termination pp.169 to 188 addition of 7.14 dma transfer timing examples p.189 modification of 7.15 (3) intervals related to dma transfer p.193 modification of remark 1 in table 8-1 interrupt/exception list p.207 modification of address in figure 8-10 in-service priority register (ispr) p.213 modification of description and diagram in 8.6 interrupt response time p.215 modification of 9.1.2 (2) (a) unit test mode p.216 modification of description of tesen and tmode1 signals in 9.2 list of test interface signals pp.217, 218 modification of 9.3 example of connection of peripheral macro in test mode p.219 modification of caution in 9.4 (1) (a) i/o pins p.220 modification of 9.4 (1) (b) handling of input pins pp.223 to 232 addition of chapter 10 NB85E901 pp.233, 234 modification of appendix a rom/ram access timing
appendix c revision history preliminary user?s manual a13971ej7v0um 250 (3) from 3rd to 4th (1/2) pages description throughout change of cgrel pin to nec reserved pin pp.34, 35 modification of 2.2.2 (14) vbwait , (15) vblast , (16) vbahld , and (19) vdselpz p.35 modification of figure 2-1 acknowledgement of dcresz signal p.38 modification of 2.2.7 (7) iramwt p.44 addition of explanation in 2.2.12 (7) ifiwrth and (8) ifiunch1 pp.52, 53 modification of description about r2 register p.61 modification of figure 3-8 data area (256 mb mode) and modification of note 2 and addition of caution p.64 deletion of caution and addition of explanation in 3.4.2 ram area p.67 addition of explanation of (5) in 3.5 peripheral i/o registers p.69 modification of imr0 to imr3 registers in 3.5.1 NB85E control registers p.71 modification of 3.5.2 memory controller (memc) control registers p.72 modification of icc registers in 3.5.3 instruction cache control registers p.72 modification of initial values in 3.5.4 data cache control registers p.77 modification of a figure in 4.2 (2) memory banks for 256 mb mode p.85 modification of figure 4-5 peripheral i/o area and programmable peripheral i/o area (b) 256 mb mode p.86 modification of caution 2 and addition of caution 5 in 4.4 programmable peripheral i/o area selection function p.88 addition of caution 1 and modification of caution 2 in 4.6 endian setting function p.91 modification of caution 1 and addition of cautions 2 to 4 in 4.7 cache configuration p.98 modification of 4.9.3 read/write timing p.116 addition of 4.9.6 misalign access timing p.121 modification of figure 5-3 peripheral i/o area and programmable peripheral i/o area (b) 256 mb mode p.122 modification of caution 2 and addition of caution 4 in 5.1 programmable peripheral i/o area p.125 modification of figure 5-6 npb strobe wait control register (vswc) p.126 modification of figure 5-7 retry function p.131 modification of figure 5-14 (a) example of write to npb peripheral macro (programmable peripheral i/o area) p.135 modification of 6.1 (1) halt mode p.136 addition of caution in 6.2.1 power save control register (psc) p.142 deletion of description about cgrel pin and modification of caution in 6.6 clock control in software/hardware stop mode p.147 addition of explanation on line transfer mode in 7.1 features p.163 addition of explanation in 7.8.1 single transfer mode p.164 addition of figure 7-14 single transfer example 3 and figure 7-15 single transfer example 4 p.166 addition of explanation in 7.8.3 line transfer mode p.167 addition of figure 7-20 line transfer example 3 and figure 7-21 line transfer example 4
appendix c revision history preliminary user?s manual a13971ej7v0um 251 (2/2) pages description p.170 addition of caution in 7.9.1 two-cycle transfer p.170 addition of caution in 7.9.2 flyby transfer pp.183 to 186 addition of a timing example of two-cycle transfer between ram connected to vdb and sdram connected to memc (nu85e502) p.203 modification of description about restored pc in remark 1 in table 8-1 interrupt/exception list p.204 modification of explanation and addition of caution in 8.2 non-maskable interrupts (nmi) pp.205, 206 modification of figure 8-1 example of non-maskable interrupt request acknowledgement operation p.208 modification of 8.2.2 restore p.217 addition of explanation in 8.3.4 (2) interrupt mask registers 0 to 3 (imr0 to imr3) pp.227, 228 deletion of description about memc dram controller (NB85E501) and change of memc sdram controller name from [NB85E502] to [nu85e502] p.230 modification of 9.4 (1) (b) handling of input pins p.231 modification of 9.5 precautions p.235 addition of caution in 10.2.2 (1) n-wire type ie connection pins and addition of explanation in (f) dbint p.239 addition of 10.2.4 pin status p.241 modification of 10.3 (9) mask function p.245 modification of remark 2 in figure 10-4 example of recommended circuit for ie connection (NB85E + NB85E901) (4) from 4th to 5th pages description pp.25, 33 modification of description about cgrel pin pp.28, 41, 85 modification of description about ifinsz1, ifinsz0 pins pp.140 to 143 addition of description about cgrel pin in 6.6 clock control in software/hardware stop mode p.226 modification of figure 9-1 peripheral macro connection example p.229 modification of 9.4 (2) test mode pins (5) from 5th to 6th (1/2) pages description pp.28, 41 modification of description on ifinsz1 and ifinsz0 pins p.29 modification of description on vplock pin p.31 modification of description on vbwrite pin p.32 modification of description on vbwait pin p.32 modification of description on vblast pin p.32 modification of description on vbahld pin
appendix c revision history preliminary user?s manual a13971ej7v0um 252 (2/2) pages description p.33 modification of description on cgrel pin p.44 modification of connection method of vbwait, vblast, and vbahld pins in 2.3 recommended connection of unused pins pp.63, 64 modification of caution and figure 3-11 peripheral i/o area in 3.4.3 peripheral i/o area p.85 modification of input levels to the ifinsz1 and ifinsz0 pins in figure 4-7 bus size configuration register (bsc) p.85 addition of example in figure 4-7 bus size configuration register (bsc) p.89 modification of cautions in 4.7 cache configuration p.96 addition of caution in 4.9.2 (6) transfer status p.96 modification of description and deletion of table 4-7 vbwrite signal in 4.9.2 (7) transfer direction p.124 modification of read timing of vpd15 to vpd0 in figure 5-7 retry function p.127 modification of timing of vpubenz in figure 5-11 read modify write timing p.138 addition of caution in 6.4 (2) (a) cancellation by interrupt request p.139 addition of table 6-3 operation after setting software stop mode in interrupt processing routine p.141 addition of caution in figure 6-4 connection of NB85E and clock control circuit p.143 addition of remark in figure 6-5 software stop mode set/cancel timing example p.184 modification of timing of vblock in figure 7-31 example of two-cycle single transfer timing (from ram connected to vdb to sdram connected to nu85e502) p.186 modification of timing of vblock and vbdc in figure 7-32 example of two-cycle single transfer timing (from sdram connected to nu85e502 to ram connected to vdb) p.231 deletion of 9.5 precautions and addition of (3) precautions when NB85E901 is connected p.235 modification of caution in 10.2.2 (1) n-wire type ie connection pins p.242 addition of note in figure 10-1 NB85E901 and NB85E connection example p.247 addition of note in figure a-1 rom access timing p.248 modification of timing of iraoz31 to iraoz0 and deletion of note in figure a-2 ram access timing p.253 addition of appendix c revision history
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